公开(公告)号：EP0803855A2

公开(公告)日：1997-10-29

申请号：EP97106459.7

申请日：1997-04-18

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi ,  Urata, Hiroyuki ,  Takata, Haruki

IPC分类号： G09G3/20

CPC分类号： G06T3/4007 ,  G09G5/005 ,  G09G5/006 ,  G09G5/008 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442

摘要： A video signal processor which includes a circuit (108) for converting the number of lines in a digitized video signal, a circuit (109) for generating a display dot clock, a circuit (110) for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit (111) for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation; frck/N = fck/M = fho where M and N are natural numbers satisfying M ≠ N .

摘要翻译： 一种视频信号处理器，其包括用于，电路（109）转换的行数在一个数字化的视频信号，用于进行行号输出婷模拟像素数据生成显示点时钟的电路（110）的电路（108） 转换并具有从所述显示不同的频率做点时钟，以及用于平滑模拟像素数据的电路（111）; 和其中显示点时钟将模拟像素数据和水平同步信号SATIS外资企业等式的频率FHO的输出频率FRK的频率FCK; $其中M和N是满足M注QUAL\; N.e自然数$

公开(公告)号：EP0534220B1

公开(公告)日：1997-08-13

申请号：EP92115281.5

申请日：1992-09-07

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Takata, Haruki ,  Konno, Mitsuo ,  Ishibashi, Kouichi ,  Kaizaki, Kazuhiro ,  Matono, Takaaki ,  Haratani, Atushi

IPC分类号： H04N5/262

CPC分类号： H04N7/0122 ,  G06T3/40 ,  H04N5/2628

公开(公告)号：EP0514819B1

公开(公告)日：1996-05-01

申请号：EP92108375.4

申请日：1992-05-18

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Takata, Haruki ,  Katsumata, Kenji ,  Hirahata, Shigeru ,  Konno, Mituo ,  Ishibashi, Kouichi ,  Suzuki, Sunao

IPC分类号： H04N5/44

CPC分类号： G06T3/4007 ,  H04N7/0122

公开(公告)号：EP0630154A2

公开(公告)日：1994-12-21

申请号：EP94109332.0

申请日：1994-06-16

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Murata, Toshinori ,  Takata, Haruki ,  Torikoshi, Shinobu ,  Eda, Takanori ,  Ishibashi, Kouichi

IPC分类号： H04N5/44

CPC分类号： H04N7/0122 ,  H04N3/27

摘要： To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).

公开(公告)号：EP0630154A3

公开(公告)日：1995-04-12

申请号：EP94109332.0

申请日：1994-06-16

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Murata, Toshinori ,  Takata, Haruki ,  Torikoshi, Shinobu ,  Eda, Takanori ,  Ishibashi, Kouichi

IPC分类号： H04N5/44

CPC分类号： H04N7/0122 ,  H04N3/27

摘要： To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal (118). A clock generating circuit (119) supplies the field memory (103) with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit (110) reads a video signal from the field memory (103) with a line period corresponding to a magnification factor and inhibits writing to a one-line memory (105) with the same period to provide a line delayed output for an output signal from the field memory (13). A vertical interpolating circuit (106) generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit (110).

摘要翻译： 通过将整个图像压缩并放大到期望的大小来提供与显示单元的屏幕的纵横比匹配的图像。 响应于来自输入端子（118）的写时钟，视频信号被顺序地写入场存储器。 时钟发生电路（119）向场存储器（103）提供具有与写入时钟的频率约高4/3倍的频率的读时钟。 垂直放大控制电路（110）以与放大率对应的行周期从场存储器（103）读取视频信号，并禁止以相同周期向单行存储器（105）写入以提供行延迟输出 用于来自场存储器（13）的输出信号。 垂直内插电路（106）根据来自垂直放大控制电路（110）的控制信号，通过内插运算产生扫描线信号。

公开(公告)号：EP0534220A3

公开(公告)日：1993-06-09

申请号：EP92115281.5

申请日：1992-09-07

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Takata, Haruki ,  Konno, Mitsuo ,  Ishibashi, Kouichi ,  Kaizaki, Kazuhiro ,  Matono, Takaaki ,  Haratani, Atushi

IPC分类号： H04N5/262

CPC分类号： H04N7/0122 ,  G06T3/40 ,  H04N5/2628

摘要： A video signal processing circuit is provided to display an image of a standard television signal on a display unit with a 16:9 aspect ratio by enlarging an image of a video signal in the horizontal and vertical directions by a magnification factor which depends on the feature of the standard television signal. The processing circuit includes a first memory circuit (104) which reads out the stored video signal in response to a read clock different from the write clock and generated by a stable frequency source so that the image of the video signal is expanded in the vertical direction, a second memory circuit (105) which implements time-base compression for the output of the first memory circuit and thereafter expands the signal, a spatial filter (106) which implements filtering for the output of the second memory circuit, an enlargement control circuit (107) which control the above-mentioned circuits, and a synchronizing processing circuit (108). The circuit arrangement enables video signals of various image sizes, such as for movie pictures, to be displayed by signal conversion on a display unit with a 16:9 aspect ratio, and is capable of suppressing jitters of video signals.

公开(公告)号：EP0534220A2

公开(公告)日：1993-03-31

申请号：EP92115281.5

申请日：1992-09-07

申请人： HITACHI, LTD.

发明人： Katsumata, Kenji ,  Hirahata, Shigeru ,  Takata, Haruki ,  Konno, Mitsuo ,  Ishibashi, Kouichi ,  Kaizaki, Kazuhiro ,  Matono, Takaaki ,  Haratani, Atushi

IPC分类号： H04N5/262

CPC分类号： H04N7/0122 ,  G06T3/40 ,  H04N5/2628

摘要： A video signal processing circuit is provided to display an image of a standard television signal on a display unit with a 16:9 aspect ratio by enlarging an image of a video signal in the horizontal and vertical directions by a magnification factor which depends on the feature of the standard television signal. The processing circuit includes a first memory circuit (104) which reads out the stored video signal in response to a read clock different from the write clock and generated by a stable frequency source so that the image of the video signal is expanded in the vertical direction, a second memory circuit (105) which implements time-base compression for the output of the first memory circuit and thereafter expands the signal, a spatial filter (106) which implements filtering for the output of the second memory circuit, an enlargement control circuit (107) which control the above-mentioned circuits, and a synchronizing processing circuit (108). The circuit arrangement enables video signals of various image sizes, such as for movie pictures, to be displayed by signal conversion on a display unit with a 16:9 aspect ratio, and is capable of suppressing jitters of video signals.

摘要翻译： 提供一种视频信号处理电路，通过以水平和垂直方向放大视频信号的图像乘以取决于特征的放大系数，在具有16:9宽高比的显示单元上显示标准电视信号的图像 的标准电视信号。 处理电路包括第一存储器电路（104），其响应于与写入时钟不同的读取时钟读出存储的视频信号，并由稳定的频率源产生，使得视频信号的图像在垂直方向上扩展 ，第二存储器电路（105），其针对所述第一存储器电路的输出实现时基压缩，然后扩展所述信号;对所述第二存储器电路的输出进行滤波的空间滤波器（106）;放大控制电路 （107），以及同步处理电路（108）。 该电路装置能够通过在具有16:9宽高比的显示单元上进行信号转换来显示诸如电影图像的各种图像尺寸的视频信号，并且能够抑制视频信号的抖动。

公开(公告)号：EP0514819A3

公开(公告)日：1993-03-03

申请号：EP92108375.4

申请日：1992-05-18

申请人： HITACHI, LTD. ,  Hitachi Video & Information System, Inc.

发明人： Takata, Haruki ,  Katsumata, Kenji ,  Hirahata, Shigeru ,  Konno, Mituo ,  Ishibashi, Kouichi ,  Suzuki, Sunao

IPC分类号： H04N5/44

CPC分类号： G06T3/4007 ,  H04N7/0122

摘要： A wide-screen television receiver capable of converting a TV signal of a non-aspect ratio into a signal of a wide aspect ratio which can be displayed on a wide screen of the wide aspect ratio and previously visually informing the user of what part of the image of the non-aspect ratio TV signal is converted in its aspect ratio and displayed on the wide screen. The receiver includes the interpolation scan speed conversion circuit (102), the mode setting circuit (104), the aspect ratio converting circuit (103), the wide cursor adding circuit 105 and the wide display (106). The interpolation scan speed conversion circuit (102) makes a series of processes such as Y/C separation and scan line interpolation for the input video signal supplied via the input terminal (101). The aspect ratio converting circuit (103) compresses the video signal from the interpolation scan speed conversion circuit (102) in the horizontal direction by use of a memory. The magnification processing circuit (109) is provided after the aspect ratio converting circuit (103). This magnification processing circuit (109) magnifies the horizontally compressed video signal so that an arbitrary part of image specified by the mode setting circuit (104) can be magnified at given magnification powers in the horizontal and vertical directions. The wide screen display (106) displays the magnified image of the video signal without horizontal and vertical distortions on the wide screen.

公开(公告)号：EP2148516B1

公开(公告)日：2010-12-29

申请号：EP09013458.6

申请日：2002-03-08

申请人： Hitachi Ltd.

发明人： Kimura, Katsunobu ,  Matono, Takaaki ,  Takata, Haruki ,  Sakai, Takeshi ,  Kato, Wataru

IPC分类号： H04N9/73

CPC分类号： H04N9/73 ,  G09G5/02 ,  G09G2320/0666

公开(公告)号：EP0803855A3

公开(公告)日：1999-06-16

申请号：EP97106459.7

申请日：1997-04-18

申请人： HITACHI, LTD.

发明人： Naka, Kazutaka ,  Maruyama, Atsushi ,  Urata, Hiroyuki ,  Takata, Haruki

IPC分类号： G09G3/20

CPC分类号： G06T3/4007 ,  G09G5/005 ,  G09G5/006 ,  G09G5/008 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442

摘要： A video signal processor which includes a circuit (108) for converting the number of lines in a digitized video signal, a circuit (109) for generating a display dot clock, a circuit (110) for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit (111) for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation; frck/N = fck/M = fho where M and N are natural numbers satisfying M ≠ N .