公开(公告)号：EP1825508A4

公开(公告)日：2009-06-24

申请号：EP05852638

申请日：2005-12-01

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

公开(公告)号：EP1842235A4

公开(公告)日：2009-03-25

申请号：EP05854758

申请日：2005-12-21

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  MARTIN DALE W ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PETERSON KIRK

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L29/7845 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region (20) and a n-type device region (10); a first-type silicide contact (30) to the n-type device region (10); the first-type silicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact (35) to the p-type device region (20); the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.