公开(公告)号：EP1825508A4

公开(公告)日：2009-06-24

申请号：EP05852638

申请日：2005-12-01

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

公开(公告)号：EP2036130A4

公开(公告)日：2009-12-23

申请号：EP07797521

申请日：2007-05-17

Applicant: IBM

Inventor： LI JINGHONG H ,  LIU YAOCHENG ,  LUO ZHIJIONG ,  MADAN ANITA ,  ROVEDO NIVO

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S257/90

公开(公告)号：EP1856725A4

公开(公告)日：2009-01-14

申请号：EP06717971

申请日：2006-01-10

Applicant: IBM

Inventor： LUO ZHIJIONG ,  FANG SUNFEI ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7833

Abstract: A process for forming a metal silicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (3) (polysilicon or amorphous silicon) is formed overlying the gate dielectric (2); a layer of metal (4) is then formed on the first layer (3), and a second layer of silicon (5) on the metal layer (4). A high-temperature (greater than 700 0C) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer (30) above the gate dielectric (2) by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer (50) from silicon in the second layer (5). The thicknesses of the layers are such that in the high-temperature processing, substantially all the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully suicided gate structure may be produced.