公开(公告)号：EP2047506A4

公开(公告)日：2012-04-25

申请号：EP07783916

申请日：2007-05-18

Applicant: IBM

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1883957A4

公开(公告)日：2008-09-17

申请号：EP06760152

申请日：2006-05-19

Applicant: IBM

Inventor： GRECO STEPHEN E ,  STANDAERT THEODORUS E

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed, hi one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit (102) using a dual damascene structure (124) in a first dielectric layer (110), and BEOL wiring over a second circuit (104) using a single damascene via structure (126) in the first dielectric layer (110). Then, simultaneously generating BEOL wiring over the first circuit (102) using a dual damascene structure (220) in a second dielectric layer (150), and BEOL wiring over the second circuit (104) using a single damascene line wire structure (160) in the second dielectric layer (150). The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.