公开(公告)号：EP4439640A1

公开(公告)日：2024-10-02

申请号：EP23209587.7

申请日：2023-11-14

申请人： Intel Corporation

发明人： MANNEBACH, Ehren ,  MILLS, Shaun ,  D'SILVA, Joseph ,  KOBRINSKY, Mauro J.

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76804 ,  H01L21/76816 ,  H01L23/522

摘要： Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.

公开(公告)号：EP3376540A1

公开(公告)日：2018-09-19

申请号：EP17162773.0

申请日：2017-03-24

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： HUANG, Yukai ,  LUOH, Tuung ,  YANG, Ta-Hung ,  CHEN, Kuang-Chao

IPC分类号： H01L27/11524 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive interface layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive interface layer.

公开(公告)号：EP3367429A1

公开(公告)日：2018-08-29

申请号：EP17158037.6

申请日：2017-02-27

申请人： IMEC vzw

发明人： LAZZARINO, Frederic

IPC分类号： H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76877

摘要： According to an aspect of the present inventive concept there is provided a method for defining patterns for conductive paths in a dielectric layer, the method comprising:
forming a mask layer above the dielectric layer,
forming above the mask layer a set of [amorphous silicon] mandrels, each mandrel having a pair of side wall spacers,
etching the mask layer, wherein the set of mandrels and the side wall spacers act as an etch mask, to form a first set of trenches in the mask layer,
covering the set of mandrels with a metal oxide planarization layer, the metal oxide planarization layer filling the first set of trenches,
etching back the metal oxide planarization layer to expose upper surfaces of the set of mandrels,
removing the set of mandrels by etching, thereby forming trenches in the metal oxide planarization layer, said trenches extending between said pairs of side wall spacers, and
etching the mask layer, wherein the metal oxide planarization layer acts as an etch mask, to form a second set of trenches in the mask layer.

公开(公告)号：EP3367428A1

公开(公告)日：2018-08-29

申请号：EP17157578.0

申请日：2017-02-23

申请人： IMEC vzw

发明人： CHAN, Boon Teik ,  MAO, Ming ,  De SCHEPPER, Peter ,  KOCSIS, Michael

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/0274 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649

摘要： A method for blocking one or more portions of one or more trenches (700) during manufacture of a semiconductor structure, the method comprising:
a. providing a substrate (100) comprising one or more trenches (700), and a dielectric material (130),
b. providing a first overlayer (300), thereby filling the one or more trenches (700);
c. covering a first area of the substrate (100), situated directly above the one or more portions and corresponding thereto, with a block pattern (400) of the condensed photo-condensable metal oxide;
d. covering the block pattern and the second area with a second overlayer (500);
e. providing a masking layer (600) over the second overlayer (500), the masking layer (600) having a via pattern (800); and
f. transferring the via pattern (800) and the other portion of the at least one of the trenches (700) into the dielectric material (130).

公开(公告)号：EP2206142B1

公开(公告)日：2018-07-18

申请号：EP08845706.4

申请日：2008-10-27

申请人： Micron Technology, Inc.

发明人： KIEHLBAUCH, Mark

IPC分类号： H01L21/033 ,  H01L21/768

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

公开(公告)号：EP3310788A1

公开(公告)日：2018-04-25

申请号：EP15895814.0

申请日：2015-06-18

申请人： INTEL Corporation

发明人： ROMERO, Patricio E.

IPC分类号： C07F1/02 ,  H01L21/205 ,  C23C16/44 ,  C23C16/455

CPC分类号： C07F15/0053 ,  C07F1/005 ,  C07F1/02 ,  C07F11/005 ,  C23C16/04 ,  C23C16/18 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897

摘要： Inherently selective precursors for deposition of second or third row transition metal (e.g., tungsten or ruthenium) thin films are described. In an example, a ligand framework for second or third row transition metal complex formation includes a lithium complex.

公开(公告)号：EP3306664A1

公开(公告)日：2018-04-11

申请号：EP16199764.8

申请日：2016-11-21

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yang, Chin-Cheng

IPC分类号： H01L27/11575 ,  H01L27/11548 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L21/76816 ,  G11C16/08 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.

摘要翻译： 诸如3D存储器阵列的多电平电路具有围绕多级区域的周边布置的一组接触区域，其中在多级电路中连接到电路元件。 每个接触区域具有其上具有着陆区域的多个台阶，包括达到数量M级别的台阶，其中数量M可以远小于W.接触区域的组合提供了所有W级别上的着陆区域 ，组合中的每个接触区域具有在W个级别的不同子集上的着陆区域。 形成器件的方法使用蚀刻修整工艺在所有接触区域中形成M电平，并且在一些接触区域中形成一个或多个各向异性蚀刻。

公开(公告)号：EP3255663A1

公开(公告)日：2017-12-13

申请号：EP16173359.7

申请日：2016-06-07

申请人： IMEC VZW

发明人： RYCKAERT, Julien ,  BÖMMELS, Jürgen ,  WILSON, Christopher

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L23/528

摘要： A method for forming a pattern for an integrated circuit, comprising the steps of:
a. providing a hardmask layer (3),
b. overlaying the hard mask layer (3) with a set of parallel material lines (41) delimiting gaps (6) therebetween,
c. providing a spacer layer (5) following the shape of the material layer (4),
d. removing a top portion (5t) of the spacer layer (5), thereby forming spacer lines (5I) alternatively separated by material lines (4I) and by gaps (6),
e. providing a blocking element (7b) in a portion of a gap (6),
f. etching selectively the hard mask layer (3) by using the material layer (4), the spacer lines (5I) and the blocking element (7b) as a mask, thereby providing a first set of parallel trenches (8) in the hardmask layer (3), wherein a trench (8a) has a blocked portion (3b), and
g. selectively removing the blocking element (7b).

摘要翻译： 一种形成集成电路图案的方法，包括以下步骤：a。 提供硬掩模层（3），b。 用一组限定其间的间隙（6）的平行材料线（41）覆盖硬掩模层（3），c。 遵循材料层（4）的形状提供间隔层（5），d。 去除间隔层（5）的顶部（5t），从而形成交替由材料线（4I）和间隙（6）分开的间隔线（5I），e。 在间隙（6）的一部分中提供阻挡元件（7b），f。 通过使用材料层（4），间隔物线（5I）和阻挡元件（7b）作为掩模选择性地刻蚀硬掩模层（3），由此在硬掩模层中提供第一组平行沟槽（8） （3），其中沟槽（8a）具有阻挡部分（3b），以及g。 选择性地移除阻挡元件（7b）。

公开(公告)号：EP3198629A1

公开(公告)日：2017-08-02

申请号：EP14902548.8

申请日：2014-09-22

申请人： Intel Corporation

发明人： CHANDHOK, Manish ,  YOUNKIN, Todd R. ,  LEE, Sang H. ,  WALLACE, Charles H.

IPC分类号： H01L21/027 ,  G03F7/20

CPC分类号： G03F7/70 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/2039 ,  G03F7/70466 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816

摘要： Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.

摘要翻译： 讨论了与多通道图案化光刻有关的技术，器件结构以及使用这种技术形成的器件。 这种技术包括用非反射辐射曝光设置在光栅图案上的抗蚀剂层，以在光栅图案的沟槽内产生增强的曝光部分，并显影抗蚀剂层以在光栅的沟槽内形成具有图案结构的图案层 模式。

公开(公告)号：EP3183743A1

公开(公告)日：2017-06-28

申请号：EP14900280.0

申请日：2014-12-22

申请人： Intel Corporation

发明人： BORODOVSKY, Yan A.

IPC分类号： H01L21/027

CPC分类号： G03F7/2037 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31769 ,  H01L21/0277 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816

摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a column for an e-beam direct write lithography tool includes a first blanker aperture array (BAA) including a staggered array of openings having a pitch along an array direction. The array direction is orthogonal to a scan direction. Each opening has a first dimension in the array direction. The column also includes a second BAA including a staggered array of openings having the pitch along the array direction. Each opening has a second dimension in the array direction, the second dimension greater than the first dimension.

摘要翻译： 描述了适合于和互补电子束光刻（CEBL）的方法的光刻设备。 在一个示例中，用于电子束直接写入光刻工具的列包括第一消隐器孔径阵列（BAA），第一消隐器孔径阵列（BAA）包括具有沿阵列方向的间距的交错开口阵列。 阵列方向与扫描方向正交。 每个开口在阵列方向上具有第一维度。 该列还包括第二BAA，其包括具有沿着阵列方向的节距的交错排列的开口。 每个开口在阵列方向上具有第二维度，第二维度大于第一维度。