-
公开(公告)号：EP4199071A1
公开(公告)日：2023-06-21
申请号：EP21214621.1
申请日：2021-12-15
摘要： Fan-out wafer-level package (1000) comprising at least one integrated circuit (100), an internal heat spreader (200) thermally connected to the integrated circuit either directly or via an interface layer (210) having a thickness in µm- or sub-µm range preferably in the range of 20 nm to 1 mm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.
-
2.发明公开
公开(公告)号：EP4345823A1
公开(公告)日：2024-04-03
申请号：EP22214910.6
申请日：2022-12-20
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik , Brandenburgische Technische Universität Cottbus-Senftenberg
摘要： A resistive random access memory (RRAM) subcell comprises a subcell circuit arrangement having an electrical series connection of interconnected or interconnectable memristors. Each of the memristors is electrically programmable to assume a selected one of a plurality of memristor states, each memristor state being associated with a respective memristor resistance value or memristor resistance-value range of the given memristor. The subcell circuit arrangement is electrically drivable to assume a selected one of a set of memory subcell states for storing information, the set of memory subcell states comprising those combinations of memristor states in the subcell circuit arrangement, which result from the electrical series connection of the memristors and have mutually distinguishable subcell resistance values or subcell resistance-value ranges. The electrical circuit arrangement of the RRAM subcell is operated using a single bitline.
-
3.发明公开
公开(公告)号：EP4024265A1
公开(公告)日：2022-07-06
申请号：EP21176328.9
申请日：2021-05-27
发明人： Kahmen, Gerhard , Grass, Eckhard
摘要： A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal.
-
公开(公告)号：EP4336683A1
公开(公告)日：2024-03-13
申请号：EP22194581.9
申请日：2022-09-08
发明人： Kahmen, Gerhard , Zimmermann, Lars
摘要： An electronic-photonic integrated precision delay-control component comprises a coarse-delay switching unit that is configured to assume one of a plurality of selectable switching states and to feed, in a given one of the switching states, an optical input signal forward to at least one of a plurality of selectable optical coarse-delay paths. A controllable fine-delay unit is configured to subject the optical input signal to a selectable fine group-delay amount that is tuneable between zero and a maximum fine group-delay amount. The coarse-delay switching unit and the fine-delay unit are arranged in a series connection to control application of a respective total group-delay amount to the optical input signal on any selectable total delay path, the total group-delay amount corresponding to a sum of the respective coarse group-delay amount and of the selectable fine group-delay amount. Co-integration of electronic components allows a complete pulse train generation on one chip with low sensitivity to perturbation, low drift and low manufacturing costs. A desired delay of individual pulses of the optical input signal can be tuned on chip with particularly high precision at particularly high pulse repetition frequencies.
-
公开(公告)号：EP4210055A1
公开(公告)日：2023-07-12
申请号：EP22150589.4
申请日：2022-01-07
发明人： Kahmen, Gerhard , Krstic, Milos
摘要： For performing in-memory multiplication of an input vector with an input matrix a storage component matrix comprises matrix memory components with a charge storage component that is tuneable by a respective matrix input signal to assume a capacitance value uniquely corresponding to an input matrix value. A vector input switch controls provision of the analog input vector signal for charging the charge storage component of the matrix memory component to a charge amount representing a mathematical product of the respective input vector value and the respective input matrix value. The matrix memory components of a column are arranged in parallel connection with each other and commonly connected in series connection with a column summation charge storage component which accumulates the charge amounts output from the charge storage components to generate a column summation output voltage indicative of a sum of the component products.
-
-
-
-
搜索结果
5 条记录 (耗时 0.015 秒)
