公开(公告)号：EP3270411A1

公开(公告)日：2018-01-17

申请号：EP17189518.8

申请日：2016-06-20

Applicant: IMEC vzw

Inventor： DE WOLF, Ingrid ,  BOEMMELS, Juergen

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76877 ,  H01L23/53295 ,  H01L24/02 ,  H01L2224/02372

Abstract: The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion. The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In the method of the invention, a mask layer is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.

Abstract translation: 本发明涉及一种用于制造集成电路器件的方法，所述集成电路器件包括前线工序（FEOL）部分和后工序后工序（BEOL）部分。 金属化层包括介电层，优选低k介电层，其中金属导体和/或互连结构结合在所述介电层内。 在本发明的方法中，在堆叠的制造期间在BEOL堆叠上或在其中一个金属化层上施加掩模层，所述掩模层覆盖部分堆叠区域并暴露所述区域的其他部分。 然后进行处理，其改变一个或多个金属化层中的电介质材料的弹性模量，但仅在未被掩模层覆盖的区域中。

公开(公告)号：EP3116022A2

公开(公告)日：2017-01-11

申请号：EP16175260.5

申请日：2016-06-20

Applicant: IMEC VZW

Inventor： DE WOLF, Ingrid ,  BÖMMELS, Jürgen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76877 ,  H01L23/53295 ,  H01L24/02 ,  H01L2224/02372

Abstract: The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion (102). The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In a device according to the invention, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In the method of the invention, a mask layer (21) is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.

Abstract translation: 本发明涉及一种方法，用于在集成电路器件产生，包括一个前端的行（FEOL）部分和后端的行（BEOL）部分（102）。 所述金属化层包括介电层，优选低k介电层，其中所述介电层内掺入金属导体和/或互连结构。 在一个设备gemäß到本发明，在至少一些所述BEOL叠层的金属化层，所述介电材料的弹性模量从层到层的一个或多个其它区域的一个区域而不同。 在发明的方法中，掩模层（21）上BEOL堆栈或在金属化层的一个堆栈的制造过程中施加，所述掩模层覆盖的堆栈区域的部分并露出所述区域的其它部分。 然后处理进行确实改变介电材料的弹性模量在一个或多个金属化层的，但只有在未覆盖掩模层的区域。

公开(公告)号：EP3116022A3

公开(公告)日：2017-03-08

申请号：EP16175260.5

申请日：2016-06-20

Applicant: IMEC VZW

Inventor： DE WOLF, Ingrid ,  BÖMMELS, Jürgen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76877 ,  H01L23/53295 ,  H01L24/02 ,  H01L2224/02372

Abstract: The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion (102). The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In a device according to the invention, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In the method of the invention, a mask layer (21) is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.

Abstract translation: 本发明涉及一种用于制造集成电路器件的方法，所述集成电路器件包括前线工序（FEOL）部分和后工序后工序（BEOL）部分（102）。 金属化层包括介电层，优选低k介电层，其中金属导体和/或互连结构结合在所述介电层内。 在根据本发明的装置中，在BEOL堆叠的至少一些金属化层中，介电材料的弹性模量从该层的一个区域到该层的一个或多个其他区域而变化。 在本发明的方法中，在堆叠的制造期间，在BEOL堆叠上或在其中一个金属化层上施加掩模层（21），所述掩模层覆盖堆叠区域的一部分并暴露所述区域的其他部分。 然后进行处理，其改变一个或多个金属化层中的电介质材料的弹性模量，但仅在未被掩模层覆盖的区域中。

公开(公告)号：EP3113215A1

公开(公告)日：2017-01-04

申请号：EP16175210.0

申请日：2016-06-20

Applicant: IMEC VZW

Inventor： DE WOLF, Ingrid ,  JAYAPALA, Murali ,  PODPOD, Arnita ,  SLABBEKOORN, John ,  BLANCH, Carolina

IPC: H01L21/66 ,  G01N21/00 ,  H01L23/00

CPC classification number: H01L22/20 ,  G01N21/00 ,  G01N21/31 ,  G05B19/418 ,  G05B2219/45031 ,  G06T7/001 ,  G06T2207/20081 ,  G06T2207/30148 ,  H01L21/02076 ,  H01L21/67253 ,  H01L21/67706 ,  H01L21/6835 ,  H01L21/6836 ,  H01L22/12 ,  H01L24/00 ,  H01L2221/68327 ,  H01L2224/1181 ,  H01L2225/06513

Abstract: A method for inspection of a semiconductor device (10) comprises: performing a processing step in manufacturing of the semiconductor device (10), wherein a compound is at least in contact with the semiconductor device (10); capturing an image on a two-dimensional image sensor (34) of an area of at least part of the semiconductor device (10), wherein the captured image (46) comprises spectral information for a plurality of positions in the area, wherein said spectral information comprises intensity of incident electromagnetic radiation for a plurality of different wavelength bands across a spectrum of wavelengths; processing the spectral information of the captured image (46) for each of the plurality of positions to determine whether residue of the compound is present in the position; and outputting information indicating positions for which residue of the compound is present for controlling a subsequent processing step in manufacturing of the semiconductor device (10).

Abstract translation: 一种用于检查半导体器件（10）的方法包括：在半导体器件（10）的制造中执行处理步骤，其中化合物至少与半导体器件（10）接触; 在所述半导体器件（10）的至少一部分的区域的二维图像传感器（34）上捕获图像，其中所述捕获图像（46）包括用于所述区域中的多个位置的光谱信息，其中所述光谱 信息包括跨越波长范围的多个不同波长带的入射电磁辐射的强度; 处理所述多个位置中的每一个的所述捕获图像（46）的光谱信息，以确定所述化合物的残留物是否存在于所述位置中; 并且输出指示所述化合物的残留物的位置的信息，以控制半导体器件（10）的制造中的后续处理步骤。