公开(公告)号：EP3010044B1

公开(公告)日：2019-02-13

申请号：EP14188713.3

申请日：2014-10-13

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Verreck, Devin ,  Verhulst, Anne S.

IPC分类号： H01L29/739 ,  H01L29/36

公开(公告)号：EP3185300A1

公开(公告)日：2017-06-28

申请号：EP15201734.9

申请日：2015-12-21

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Verhulst, Anne S. ,  Verreck, Devin ,  Alian, AliReza

IPC分类号： H01L29/739

CPC分类号： H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

摘要： A Tunnel Field-Effect Transistor (TFET 100) comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region (102) doped with a dopant element having a first dopant type and a first doping concentration; a drain region (101) doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region (103) situated between the source region (102) and the drain region (101, 501) and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack (110) comprising a gate electrode (111) on a gate dielectric layer (112), the gate stack (110) covering at least part of the channel region (103) and extending at the source side up to at least an interface between the source region (102) and the channel region (103), a drain extension region (105) in the channel region (103) or on top thereof, the drain extension region (105) being formed from a material suitable for creating, and having a length / thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

摘要翻译： 一种包括源 - 沟道 - 漏极结构的隧道场效应晶体管（TFET 100），所述源 - 沟道 - 漏极结构包括掺杂有具有第一掺杂剂类型和第一掺杂浓度的掺杂剂元素的源极区域（102） 掺杂有具有与第一掺杂剂类型相反的第二掺杂剂类型的掺杂剂元素和第二掺杂浓度的漏极区（101），位于源极区（102）和漏极区（101）之间的沟道区（103） ，501），并且具有低于源极和漏极区的掺杂浓度的本征掺杂浓度或低掺杂浓度;包括在栅极电介质层（112）上的栅极电极（111）的栅极叠层（110）;所述 栅极叠层110覆盖沟道区103的至少一部分并且在源极侧延伸至源极区102和沟道区103之间的至少一个界面;漏极延伸区105， 在沟道区（103）中或在其顶部上，漏极延伸区（105）由适于产生的材料形成，并且具有长度/厚度比，使得在使用中其在OFF中产生带电层 - TFET的状态，与电荷o相反 f漏极区域的多数载流子。

公开(公告)号：EP3010044A1

公开(公告)日：2016-04-20

申请号：EP14188713.3

申请日：2014-10-13

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Verreck, Devin ,  Verhulst, Anne S.

IPC分类号： H01L29/739 ,  H01L29/36

CPC分类号： H01L29/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/365 ,  H01L29/42356 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78

摘要： A p-type Tunnel Field-Effect Transistor (p-TFET) comprises a drain p-type semiconductor region (101), a source n-type semiconductor region (103, 503), and at least one gate stack (104, 504). The source n-type semiconductor region (103, 503, 603) comprises a lowly doped section (109, 509, 609) with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×10 18 at/cm 3 and, in contact with the lowly doped section, a highly doped section (111, 511) with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 5×10 18 at/cm 3 .

摘要翻译： p型隧道场效应晶体管（p-TFET）包括漏极p型半导体区域（101），源极n型半导体区域（103,503）和至少一个栅极叠层（104,504） 。 源极n型半导体区域（103,503,603）包括长度为至少10nm的低掺杂部分（109,509,609），并且n型掺杂元素的掺杂水平低于5×10 18 在/ cm 3处，并且与低掺杂部分接触，具有在1单层和20nm之间的长度的高掺杂部分（111,511），并且具有高于5×10 18的n型掺杂元素的掺杂水平， 厘米3。

公开(公告)号：EP4345825A1

公开(公告)日：2024-04-03

申请号：EP22198979.1

申请日：2022-09-30

申请人： Imec VZW

发明人： Verreck, Devin ,  Rosmeulen, Maarten

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08

摘要： This disclosure is concerned with NAND flash memory, and proposes a method for programming the NAND flash memory. The NAND flash memory comprises a semiconductor channel layer, a first gate on a first side of the channel layer, and a plurality of second gates on a second side of the channel layer. Each second gate is associated with one memory cell and connected to one word line. The method comprises applying a first voltage to the first gate, and a pass voltage to one or more word lines, to allow charge to inject into the channel layer and form charge packets. Each charge packet is arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines, to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.