利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.013 秒)

    PROGRAMMABLE LOGIC DEVICES AND CONFIGURABLE LOGIC NETWORKS
    1.
    发明公开
    PROGRAMMABLE LOGIC DEVICES AND CONFIGURABLE LOGIC NETWORKS 失效
    可编程逻辑器件和可配置逻辑网络。

    公开(公告)号：EP0669057A1

    公开(公告)日：1995-08-30

    申请号：EP94901341.0

    申请日：1993-11-08

    申请人： INFINITE TECHNOLOGY CORPORATION ,  NIPPON PRECISION CIRCUITS INC.

    发明人： JENNINGS, Earle, W., III ,  LANDERS, George, Herman

    IPC分类号： H03K19

    CPC分类号： H03K19/17712

    摘要： A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which can then be used to provide inputs to programmable logic networks (POR, UCL,...) for implementing logic functions of various types and functionality. Each programmable logic device includes an AND logic array (FAND...) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG...) having inputs for receiving signals and generating sum term output signals (OF...). One or both of the AND logic and OR logic arrays is programmable and the logic arrays are interconnected to apply output signals from one of them as input signals to the other one, the output from which provides PLD output signals. The logic combination networks may be fixed logic networks (LCN100) or programmable logic function generators (UBLFG20, UBFF2P) that produce outputs controlled by a set of programmable inputs (CNx, DNx) to the generator as a function of the logic inputs (O, P) received from the programmable logic devices.

    PROGRAMMABLE LOGIC NETWORKS
    2.
    发明公开
    PROGRAMMABLE LOGIC NETWORKS 失效
    可编程逻辑网络。

    公开(公告)号：EP0669055A1

    公开(公告)日：1995-08-30

    申请号：EP94901340.0

    申请日：1993-11-08

    申请人： INFINITE TECHNOLOGY CORPORATION ,  NIPPON PRECISION CIRCUITS INC.

    发明人： JENNINGS, Earle, W., III ,  LANDERS, George, Herman

    IPC分类号： G06F15 ,  G06F17 ,  H03K19

    CPC分类号： H03K19/17704

    摘要： A logic system comprising one or more logic networks (LNA0..LNA3) that can perform a variety of logic functions, either by configuration of a multi-function network or by a switched network comprising several sub-networks each of which performs one or more dedicated logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits (PROG) from which that logic network receives logic control signals (LSFA0..LSFA3) to select a particular logic function or functions to be performed by the logic network(s). The programmable circuit also supplies separate logic signals (LSCA0..LSCA3) to control the operation of the logic network(s) in implementing the selected logic function. In this manner the programmable circuit (PROG) can essentially be dedicated to selecting the function and controlling the operation of the selected function of the logic network(s) and is relieved of significant functional overhead associated with data manipulation typically performed by conventional operation of logic network(s). This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.