公开(公告)号：EP3005127A4

公开(公告)日：2017-01-25

申请号：EP14808307

申请日：2014-05-30

申请人： INTEL CORP

发明人： PATEL BAIJU V ,  LI XIAONING ,  ANVIN H P ,  MALLICK ASIT K ,  NEIGER GILBERT ,  CROSSLAND JAMES B ,  OPFERMAN TOBY ,  KHARE ATUL A ,  BRANDT JASON W ,  COKE JAMES S ,  VAJDA BRIAN L

IPC分类号： G06F12/14 ,  G06F9/30 ,  G06F9/45 ,  G06F12/02 ,  G06F21/52

CPC分类号： G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

摘要翻译： 示例性处理系统可以包括：下层堆栈绑定寄存器，被配置为存储第一存储器地址，第一存储器地址标识经由堆栈段可寻址的存储器的下限; 上堆栈绑定寄存器，被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 以及堆栈边界检查逻辑，其被配置为通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来检测未授权堆栈的转动。

公开(公告)号：EP2761469A4

公开(公告)日：2015-07-01

申请号：EP11873493

申请日：2011-09-30

申请人： INTEL CORP

发明人： PUTHIYEDATH LEENA K ,  FANNING BLAISE ,  OPFERMAN TONY ,  CROSSLAND JAMES B

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F9/44 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F13/14 ,  G06F13/16

CPC分类号： G06F3/0679 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0644 ,  G06F12/0238 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0866 ,  G06F2212/2024 ,  G06F2212/214 ,  G06F2212/251 ,  G06F2212/7201

摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte -rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.