公开(公告)号：EP3005127A4

公开(公告)日：2017-01-25

申请号：EP14808307

申请日：2014-05-30

申请人： INTEL CORP

发明人： PATEL BAIJU V ,  LI XIAONING ,  ANVIN H P ,  MALLICK ASIT K ,  NEIGER GILBERT ,  CROSSLAND JAMES B ,  OPFERMAN TOBY ,  KHARE ATUL A ,  BRANDT JASON W ,  COKE JAMES S ,  VAJDA BRIAN L

IPC分类号： G06F12/14 ,  G06F9/30 ,  G06F9/45 ,  G06F12/02 ,  G06F21/52

CPC分类号： G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

摘要翻译： 示例性处理系统可以包括：下层堆栈绑定寄存器，被配置为存储第一存储器地址，第一存储器地址标识经由堆栈段可寻址的存储器的下限; 上堆栈绑定寄存器，被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 以及堆栈边界检查逻辑，其被配置为通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来检测未授权堆栈的转动。

公开(公告)号：EP3210123A4

公开(公告)日：2018-05-09

申请号：EP15851712

申请日：2015-08-19

申请人： INTEL CORP

发明人： KOUFATY DAVID A ,  NEIGER GILBERT ,  SANKARAN RAJESH M ,  ANDERSON ANDREW V ,  DULLOOR SUBRAMANYA R ,  HAAS WERNER ,  NUZMAN JOSEPH

IPC分类号： G06F12/14 ,  G06F12/10 ,  G06F21/52

CPC分类号： G06F12/1466 ,  G06F21/52 ,  G06F2212/1052

摘要： A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

公开(公告)号：EP3198402A4

公开(公告)日：2018-06-20

申请号：EP15843881

申请日：2015-08-31

申请人： INTEL CORP

发明人： ANVIN H PETER ,  NEIGER GILBERT

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F11/07 ,  G06F13/24

CPC分类号： G06F13/24 ,  G06F9/327 ,  G06F9/4812 ,  G11C7/1072

摘要： A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：EP3049992A4

公开(公告)日：2017-05-03

申请号：EP14849831

申请日：2014-09-16

申请人： INTEL CORP

发明人： CHHABRA SIDDHARTHA ,  SAVAGAONKAR UDAY R ,  GOLDSMITH MICHAEL A ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  MAKARAM RAGHUNANDAN ,  ROZAS CARLOS V ,  SANTONI AMY L ,  SCARLATA VINCENT R ,  SHANBHOGUE VEDVYAS ,  SMITH WESLEY H ,  ANATI ITTAI ,  ALEXANDROVICH ILYA

IPC分类号： G06F21/79 ,  G06F12/14

CPC分类号： G06F12/1408 ,  G06F9/45558 ,  G06F12/0808 ,  G06F12/0897 ,  G06F12/1027 ,  G06F2009/45587 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/152

摘要： Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.

摘要翻译： 描述了安全内存重新分区技术。 处理器包括处理器核心和耦合在处理器核心与主存储器之间的存储器控​​制器。 主存储器包括一个存储器范围，包括一部分可转换页面可转换为安全页面或非安全页面。 响应于页面转换指令，处理器核心根据指令确定要转换的存储器范围中的可转换页面并将可转换页面转换为安全页面或非安全页面中的至少一个。 存储器范围还可以包括响应于区段转换指令而可转换的硬件保留区段。