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公开(公告)号：EP3504629A1
公开(公告)日：2019-07-03
申请号：EP17847142.1
申请日：2017-07-21
申请人： Intel Corporation
发明人： HILDESHEIM, Gur , NEIGER, Gilbert , PATEL, Baiju V. , RAIS, Ron
IPC分类号： G06F12/14
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2.发明公开PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO SUPPORT LIVE MIGRATION OF PROTECTED CONTAINERS 审中-公开处理器，方法，系统和说明，以支持受保护的容器的实时迁移
公开(公告)号：EP3314853A1
公开(公告)日：2018-05-02
申请号：EP16814991.2
申请日：2016-05-27
申请人： Intel Corporation
发明人： ROZAS, Carlos V. , VIJ, Mona , LESLIE-HURD, Rebekah M. , ZMUDZINSKI, Krystof C. , CHAKRABARTI, Somnath , MCKEEN, Francis X. , SCARLATA, Vincent R. , JOHNSON, Simon P. , ALEXANDROVICH, Ilya , NEIGER, Gilbert , SHANBHOGUE, Vedvyas , ANATI, Ittai
CPC分类号： G06F12/1408 , G06F8/41 , G06F9/30145 , G06F9/45558 , G06F21/53 , G06F21/602 , G06F2009/4557 , G06F2009/45587 , G06F2212/1052
摘要： A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
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公开(公告)号：EP3238084A1
公开(公告)日：2017-11-01
申请号：EP15873910.2
申请日：2015-11-12
申请人： Intel Corporation
CPC分类号： G06F13/34
摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.
摘要翻译： 向用户级应用程序提供中断的系统和方法。 一种示例处理系统包括：存储器，被配置为存储与由处理系统执行的多个用户级应用对应的多个用户级APIC数据结构和多个用户级中断处理机地址数据结构; 以及处理内核，被配置为响应于接收到用户级中断的通知，设置待定中断位标志，所述待决中断位标志具有由与用户级中断相关联的用户级APIC数据结构中的用户级中断的标识符定义的位置 由处理核心当前正在执行的用户级应用程序，并且调用由与用户级应用程序相关联的用户级中断处理程序地址数据结构标识的用户级中断处理程序，用于具有 用户级APIC数据结构所标识的一个或多个未决用户级中断中的最高优先级。
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公开(公告)号：EP4120070A1
公开(公告)日：2023-01-18
申请号：EP22193012.6
申请日：2016-12-31
申请人： INTEL Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/30
摘要： The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.
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公开(公告)号：EP3457311B1
公开(公告)日：2020-02-26
申请号：EP18189207.6
申请日：2018-08-15
申请人： INTEL Corporation
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公开(公告)号：EP3520010A1
公开(公告)日：2019-08-07
申请号：EP17857145.1
申请日：2017-08-30
申请人： Intel Corporation
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公开(公告)号：EP3005127B1
公开(公告)日：2018-06-27
申请号：EP14808307.4
申请日：2014-05-30
申请人： Intel Corporation
发明人： PATEL, Baiju V. , LI, Xiaoning , ANVIN, H. P. , MALLICK, Asit K. , NEIGER, Gilbert , CROSSLAND, James B. , OPFERMAN, Toby , KHARE, Atul A. , BRANDT, Jason W. , COKE, James S. , VAJDA, Brian L.
CPC分类号： G06F12/145 , G06F8/434 , G06F9/30105 , G06F9/30134 , G06F21/52
摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.
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公开(公告)号：EP3049992A1
公开(公告)日：2016-08-03
申请号：EP14849831.4
申请日：2014-09-16
申请人： Intel Corporation
发明人： CHHABRA, Siddhartha , SAVAGAONKAR, Uday R. , GOLDSMITH, Michael A. , JOHNSON, Simon P. , LESLIE-HURD, Rebekah M. , MCKEEN, Francis X. , NEIGER, Gilbert , MAKARAM, Raghunandan , ROZAS, Carlos V. , SANTONI, Amy L. , SCARLATA, Vincent R. , SHANBHOGUE, Vedvyas , SMITH, Wesley H. , ANATI, Ittai , ALEXANDROVICH, Ilya
CPC分类号： G06F12/1408 , G06F9/45558 , G06F12/0808 , G06F12/0897 , G06F12/1027 , G06F2009/45587 , G06F2212/1032 , G06F2212/1048 , G06F2212/152
摘要： Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.
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公开(公告)号：EP3005127A1
公开(公告)日：2016-04-13
申请号：EP14808307.4
申请日：2014-05-30
申请人： Intel Corporation
发明人： PATEL, Baiju V. , LI, Xiaoning , ANVIN, H. P. , MALLICK, Asit K. , NEIGER, Gilbert , CROSSLAND, James B. , OPFERMAN, Toby , KHARE, Atul A. , BRANDT, Jason W. , COKE, James S. , VAJDA, Brian L.
CPC分类号： G06F12/145 , G06F8/434 , G06F9/30105 , G06F9/30134 , G06F21/52
摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.
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