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    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS
    1.
    发明公开
    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS 审中-公开

    公开(公告)号：EP4141661A1

    公开(公告)日：2023-03-01

    申请号：EP22200756.9

    申请日：2019-06-26

    申请人： Intel Corporation

    发明人： TOLL, Bret ,  HUGHES, Christopher J. ,  BAUM, Dan ,  OULD-AHMED-VALL, Elmoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

    IPC分类号： G06F9/30

    摘要： Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, an apparatus comprises a configuration storage to store configuration information for a two-dimensional (2D) matrix storage, the configuration information to include a first value indicative of a number of rows of the 2D matrix storage and a second value indicative of a number of columns of the 2D matrix storage, fetch circuitry to fetch an instruction, the instruction to specify the 2D matrix storage, a row of the 2D matrix storage, and a 512-bit vector register, decode circuitry, coupled with the fetch circuitry, to decode the instruction, and execution circuitry, coupled with the decode circuitry, to perform operations corresponding to the instruction, including to store the row of the 2D matrix storage to the 512-bit vector register.

    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS
    3.
    发明公开
    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS 审中-公开

    公开(公告)号：EP3629154A3

    公开(公告)日：2020-05-06

    申请号：EP19182737.7

    申请日：2019-06-26

    申请人： INTEL Corporation

    发明人： TOLL, Bret ,  HUGHES, Christopher J. ,  BAUM, Dan ,  OULD-AHMED-VALL, Elmoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

    IPC分类号： G06F9/30

    摘要： Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE
    4.
    发明公开
    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE 审中-公开
    用于执行矢量位解压的方法和设备

    公开(公告)号：EP3238035A1

    公开(公告)日：2017-11-01

    申请号：EP15874023.3

    申请日：2015-11-25

    申请人： Intel Corporation

    发明人： OULD-AHMED-VALL, Elmoustapha ,  CORBAL, Jesus ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  SOLE, Guillem ,  ESPASA, Roger

    IPC分类号： G06F9/30

    摘要： A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

    摘要翻译： 一种用于执行矢量比特混洗的装置和方法。 例如，处理器的一个实施例包括：第一矢量寄存器，用于存储多个源数据元素; 第二矢量寄存器，用于存储多个控制元件，每个控制元件包括多个位字段，每个位字段与目的地掩码寄存器中的相应位位置相关联，并且识别来自每个源的位 要复制到每个特定位位置的数据元素; 以及向量位混洗逻辑，以从第二向量寄存器中读取每个位字段以识别来自每个源数据元素的位，并且响应地将来自每个源数据元素的位复制到目的地掩码中的每个对应位位置 寄存器。

    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL
    5.
    发明公开
    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL 审中-公开
    用于执行矢量位反转的方法和设备

    公开(公告)号：EP3238030A1

    公开(公告)日：2017-11-01

    申请号：EP15873967.2

    申请日：2015-11-23

    申请人： Intel Corporation

    发明人： CORBAL, Jesus ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CHARNEY, Mark J.

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

    摘要： An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; vector bit reversal logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the source vector register to generate a set of reversed bit groups; and a destination vector register to store the reversed bit groups.

    摘要翻译： 一种执行矢量位反转的设备和方法。 例如，处理器的一个实施例包括：源矢量寄存器，用于存储多个源比特组，其中用于比特组的大小将在指令的立即指定; 矢量比特反转逻辑，用于从源向量寄存器内的连续比特组的立即位置和响应反向位置确定比特组大小，以生成一组反转比特组; 和一个目标矢量寄存器来存储反转的位组。

    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL AND CROSSING
    6.
    发明公开
    METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL AND CROSSING 审中-公开
    用于执行矢量位反转和交叉的方法和设备

    公开(公告)号：EP3238029A1

    公开(公告)日：2017-11-01

    申请号：EP15873966.4

    申请日：2015-11-23

    申请人： Intel Corporation

    发明人： CORBAL, Jesus ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CHARNEY, Mark J.

    IPC分类号： G06F9/30 ,  G06F9/06

    CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30032

    摘要： An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

    摘要翻译： 一种执行矢量位反转和交叉的装置和方法。 例如，处理器的一个实施例包括：第一源向量寄存器，用于存储第一多个源位组，其中用于位组的大小将在指令的立即指定; 第二源向量，用于存储第二多个源比特组; 矢量位反转和交叉逻辑，以从第一源矢量寄存器内的连续位组的立即位置和响应反向位置确定位组大小，以生成一组反转位组，其中矢量位反转和交叉逻辑另外 将该组反转比特组与第二多个比特组交织; 以及目的地矢量寄存器，用于存储与第一多个比特组交织的反转比特组。

    APPARATUS AND METHOD FOR VECTOR PACKED MULTIPLY OF SIGNED AND UNSIGNED WORDS
    9.
    发明公开
    APPARATUS AND METHOD FOR VECTOR PACKED MULTIPLY OF SIGNED AND UNSIGNED WORDS 审中-公开

    公开(公告)号：EP4109246A1

    公开(公告)日：2022-12-28

    申请号：EP22166208.3

    申请日：2022-03-31

    申请人： Intel Corporation

    发明人： MADDURI, Venkateswara Rao ,  VALENTINE, Robert ,  CHARNEY, Mark J.

    IPC分类号： G06F9/30

    摘要： An apparatus and method for performing a vector packed multiplication of signed and unsigned words. For example, one embodiment of a processor includes a decoder to decode a vector packed multiply instruction having operands to identify a first and a second plurality of packed words, first and second source registers to store the first and second plurality of packed words, and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply each packed word in the first source register with a corresponding packed word in the second source register to generate a plurality of doubleword products and rounding circuitry to round each of the doubleword products according to a rounding method to generate a plurality of rounded doubleword products. Each upper word of the rounded doubleword results is then stored into a corresponding word data element positions of a destination register.