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1.
公开(公告)号:EP1151383A1
公开(公告)日:2001-11-07
申请号:EP99937784.9
申请日:1999-08-03
申请人: INTEL CORPORATION
发明人: SAGER, David, J.
IPC分类号: G06F12/02
摘要: A content addressable memory (200) compares the value of redundant form input data to non-redundant form values stored in registers (220s) of the memory. The memory decodes the redundant form input data in a data decoder (210). Thereafter, the CAM performs match detection on the decoded data. The decoding and match detection are performed more quickly than traditional adders and even more quickly than complete redundant form adders.
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公开(公告)号:EP1129409A2
公开(公告)日:2001-09-05
申请号:EP99965886.7
申请日:1999-08-27
申请人: INTEL CORPORATION
发明人: SAGER, David, J.
IPC分类号: G06F12/00
CPC分类号: G11C8/00
摘要: The present invention provides a memory system (200) that retrieves data based upon redundant form address data. The memory system (200) includes a memory (220) having a plurality of memory lines (222) and an address decoder (210) that enables one of the memory lines (222) in response to a redundant form address signal. A redundant form decoder (230) decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder (230) avoids a completion add that would otherwise be required, yielding very fast access to memory.
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3.
公开(公告)号:EP1151383B1
公开(公告)日:2006-12-20
申请号:EP99937784.9
申请日:1999-08-03
申请人: INTEL CORPORATION
发明人: SAGER, David, J.
IPC分类号: G06F12/02
摘要: A content addressable memory (200) compares the value of redundant form input data to non-redundant form values stored in registers (220s) of the memory. The memory decodes the redundant form input data in a data decoder (210). Thereafter, the CAM performs match detection on the decoded data. The decoding and match detection are performed more quickly than traditional adders and even more quickly than complete redundant form adders.
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公开(公告)号:EP1129409B1
公开(公告)日:2004-11-24
申请号:EP99965886.7
申请日:1999-08-27
申请人: INTEL CORPORATION
发明人: SAGER, David, J.
CPC分类号: G11C8/00
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公开(公告)号:EP1334426A2
公开(公告)日:2003-08-13
申请号:EP01986210.1
申请日:2001-10-18
申请人: INTEL CORPORATION
发明人: CARMEAN, Douglas, M. , BOGGS, Darrell, D. , SAGER, David, J. , MCKEEN, Francis, X. , HAMMARLUND, Per , SINGHAL, Ronak
IPC分类号: G06F9/38
CPC分类号: G06F9/3842 , G06F9/3861
摘要: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
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公开(公告)号:EP1198747A1
公开(公告)日:2002-04-24
申请号:EP99902317.9
申请日:1999-01-15
申请人: INTEL CORPORATION
IPC分类号: G06F9/38
CPC分类号: G06F9/3808 , G06F9/3802 , G06F9/3836 , G06F12/0875
摘要: A cache memory (10) is constituted with a data array (14) and control logic (26). The data array (14) includes a number of data lines, and the control logic (26) operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more basic blocks of instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
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公开(公告)号:EP1145114A1
公开(公告)日:2001-10-17
申请号:EP99967333.8
申请日:1999-12-16
申请人: INTEL CORPORATION
IPC分类号: G06F9/38
CPC分类号: G06F9/3865 , G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要: A computer processor that has a checker for receiving an instruction. The checker includes a scoreboard, an input for receiving an external replay signal, and decision logic coupled to the scoreboard and the input. The decision logic determines whether the instruction executed correctly based on both the scoreboard and the external replay signal.
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