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    APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS
    1.
    发明公开
    APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS 审中-公开
    DEVICE AND METHOD FOR命令重新安排规划

    公开(公告)号：EP1334426A2

    公开(公告)日：2003-08-13

    申请号：EP01986210.1

    申请日：2001-10-18

    申请人： INTEL CORPORATION

    发明人： CARMEAN, Douglas, M. ,  BOGGS, Darrell, D. ,  SAGER, David, J. ,  MCKEEN, Francis, X. ,  HAMMARLUND, Per ,  SINGHAL, Ronak

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3842 ,  G06F9/3861

    摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    PROCESSORS, METHODS, AND SYSTEMS TO ACCESS A SET OF REGISTERS AS EITHER A PLURALITY OF SMALLER REGISTERS OR A COMBINED LARGER REGISTER
    2.
    发明公开
    PROCESSORS, METHODS, AND SYSTEMS TO ACCESS A SET OF REGISTERS AS EITHER A PLURALITY OF SMALLER REGISTERS OR A COMBINED LARGER REGISTER 审中-公开
    处理器，方法和访问寄存器的任一组几个较小的寄存器的形式或组合BIGGER注册Systems

    公开(公告)号：EP3014419A1

    公开(公告)日：2016-05-04

    申请号：EP14818729.7

    申请日：2014-06-26

    申请人： Intel Corporation

    发明人： TOLL, Bret L. ,  SINGHAL, Ronak ,  GUY, Buford M. ,  NAIK, Mishali

    IPC分类号： G06F9/06 ,  G06F9/30

    CPC分类号： G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30192

    摘要： A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.

    摘要翻译： 一个形态的处理器包括一组能够存储压缩数据的寄存器。 执行单元耦接于该组寄存器。 所述执行单元访问该组寄存器中的至少两种不同的方式响应于指令。 所述至少两种不同的方式包括其中该组寄存器是表示N位寄存器的多个A第一种方式。 所述至少两种不同的方式，以便包括其中该组寄存器是代表至少2N比特的单个寄存器的第二方式。 在一个方面，所述至少2N个位是为至少256位。

    PACKED DATA ELEMENT PREDICATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    3.
    发明公开
    PACKED DATA ELEMENT PREDICATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    处理器适用于预测打包数据元素，方法，系统和指令

    公开(公告)号：EP3014418A1

    公开(公告)日：2016-05-04

    申请号：EP14818406.2

    申请日：2014-06-17

    申请人： Intel Corporation

    发明人： GUY, Buford M. ,  SINGHAL, Ronak ,  NAIK, Mishali ,  TOLL, Bret L.

    IPC分类号： G06F9/06 ,  G06F9/30

    摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    5.
    发明公开
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开
    SPEICHERZUGRIFFSBEFEHLE，-PROZESSOREN，-VERFAHREN，UND -SYSTEME MIT MEHREREN REGISTERN

    公开(公告)号：EP3014416A1

    公开(公告)日：2016-05-04

    申请号：EP14817022.8

    申请日：2014-06-26

    申请人： Intel Corporation

    发明人： HINTON, Glenn ,  TOLL, Bret ,  SINGHAL, Ronak

    IPC分类号： G06F9/06 ,  G06F12/08

    CPC分类号： G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    摘要： A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an MxN-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the MxN-bits of the line of memory.

    摘要翻译： 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多个寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器访问操作。 该操作涉及在包括所指示的寄存器的每个N位寄存器中涉及N位数据。 操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器存取操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。