公开(公告)号：EP3284089A1

公开(公告)日：2018-02-21

申请号：EP16780406.1

申请日：2016-02-10

申请人： INTEL Corporation

发明人： DUDULWAR, Pankaj Vinayak ,  BANDI, Chenchu Punnarao ,  TEH, Lip Khoon ,  TAN, Tat Hin

IPC分类号： G11C7/06 ,  G11C5/14

CPC分类号： H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

摘要： Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.