公开(公告)号：EP3147908A1

公开(公告)日：2017-03-29

申请号：EP15186601.9

申请日：2015-09-24

申请人： IMEC VZW

发明人： CATTHOOR, Francky ,  RAGHAVAN, Praveen ,  HARTMANN, Matthias ,  KOMALAN PERUMKUNNIL, Manu ,  GÓMEZ, José Ignacio ,  TENLLADO, Christian

IPC分类号： G11C7/10 ,  G06F12/08 ,  G11C11/16

CPC分类号： G06F12/0811 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F3/0688 ,  G06F8/41 ,  G06F8/452 ,  G06F9/30036 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/0897 ,  G06F13/1657 ,  G06F13/1673 ,  G06F15/781 ,  G06F15/7846 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/601 ,  G06F2212/6028 ,  G11C7/10 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675

摘要： The present invention relates to a memory hierarchy being directly connectable to a processor, said memory hierarchy having at least a Level 1, hereinafter termed L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB), said buffer structure comprising a plurality of interconnected wide registers with an asymmetric organization, wider towards said non-volatile memory unit than towards a data path connectable to said processor, said buffer structure and said non-volatile memory unit arranged for being directly connectable to said processor so that data words are selectable to be read or written by said processor.

摘要翻译： 本发明涉及一种存储器层级直接连接到处理器，所述具有至少一个第1级，其包括非易失性存储器单元为L1数据存储器和缓冲结构称为L1存储器结构之后开始（L1 VWB存储器层级 ），所述缓冲结构包括与在不对称组织互连宽寄存器复数，抗蚀剂对所述非易失性存储器单元比朝向连接到所述处理器，所述缓冲结构和被布置为直接地连接所述非易失性存储器单元的数据路径 所述处理器象数据字被选择以进行读取或由所述处理器写入。

公开(公告)号：EP2831880A4

公开(公告)日：2015-12-09

申请号：EP12872781

申请日：2012-03-25

申请人： INTEL CORP

发明人： RAYCHOWDHURY ARIJIT ,  KENCKE DAVID ,  DOYLE BRIAN ,  KUO CHARLES ,  TSCHANZ JAMES ,  HAMZAOGLU FATIH ,  WANG YIH ,  GOLIZADEH MOJARAD ROKSANA

IPC分类号： G11C11/16

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

公开(公告)号：EP2740123A4

公开(公告)日：2015-07-22

申请号：EP12819702

申请日：2012-07-19

申请人： UNIV RAMOT

发明人： GERBER ALEXANDER ,  SEGAL AMIR

IPC分类号： G11C11/18 ,  G01R15/20 ,  G11C11/16

CPC分类号： G01R33/07 ,  G01R15/202 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C11/5607

公开(公告)号：EP2625689B1

公开(公告)日：2014-07-09

申请号：EP11773945.8

申请日：2011-10-10

申请人： Qualcomm Incorporated

发明人： LEE, Kangho ,  KIM, Tae Hyun ,  LI, Xia ,  KIM, Jung Pill ,  KANG, Seung H.

IPC分类号： G11C11/16 ,  G11C5/08 ,  G11C5/02 ,  H01L27/02

CPC分类号： G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

公开(公告)号：EP2740123A1

公开(公告)日：2014-06-11

申请号：EP12819702.7

申请日：2012-07-19

申请人： Ramot at Tel Aviv University, Ltd.

发明人： GERBER, Alexander ,  SEGAL, Amir

IPC分类号： G11C11/18

CPC分类号： G01R33/07 ,  G01R15/202 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C11/5607

摘要： A device (20) for storing data includes at least first and second ferromagnetic films (F1, F2) and a sensing circuit (28). The ferromagnetic films both have perpendicular magnetic anisotropy that is configured responsively to the stored data, and are connected so that an electrical current traverses the first and second ferromagnetic films and generates respective first and second extraordinary Hall voltages therein. The sensing circuit is configured to read out the stored data by measuring the first and second extraordinary Hall voltages.

公开(公告)号：EP2625689A1

公开(公告)日：2013-08-14

申请号：EP11773945.8

申请日：2011-10-10

申请人： Qualcomm Incorporated

发明人： LEE, Kangho ,  KIM, Tae Hyun ,  LI, Xia ,  KIM, Jung Pill ,  KANG, Seung H.

IPC分类号： G11C5/02 ,  H01L27/02

CPC分类号： G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

摘要： A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

公开(公告)号：EP2831880B1

公开(公告)日：2017-03-15

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/16

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

公开(公告)号：EP2831880A1

公开(公告)日：2015-02-04

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/15

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

公开(公告)号：EP2583281A1

公开(公告)日：2013-04-24

申请号：EP11729763.0

申请日：2011-06-16

申请人： Centre National de la Recherche Scientifique ,  Ecole Centrale De Lille

发明人： TIERCELIN, Nicolas ,  DUSCH, Yannick ,  PERNOD, Philippe Jacques ,  PREOBRAZHENSKY, Vladimir

IPC分类号： G11C11/16 ,  G11C11/56

CPC分类号： G11C11/14 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1675 ,  G11C11/2275 ,  G11C11/5607 ,  H01L27/20

摘要： Magnetoelectric memory element comprising: a magnetic element (ELM) that has two equilibrium directions (P
1 , P
2 ) in which its magnetization is stable, these direction not being mutually opposed; a piezoelectric or electrostrictive substrate (SP) mechanically coupled to said magnetic element; and a least a first electrode (EL
1 ) and a second electrode (EL
2 ), arranged so as to apply an electric field to the piezoelectric or electrostrictive substrate such that said substrate exerts on said magnetic element a non-isotropic mechanical stress, able to induce switching of the magnetization state of said magnetic element by magnetostrictive coupling. Memory cell comprising such a memory element. Direct-access non-volatile memory and programmable logic circuit comprising a plurality of such memory cells.

摘要翻译： 磁电存储元件包括具有沿着第一轴对准的容易磁化轴的磁性元件，用于向磁性元件施加沿着不平行于第一轴线的第二轴对准的磁极化场的装置，与第一轴不平行的压电或电致伸缩衬底， 所述磁性元件以及布置成向所述基板施加电场的第一和第二电极，使得所述基板在所述磁性元件上施加主方向的非各向同性机械应​​力，所述主方向通常沿着与第一 和第二轴。 磁性元件通过磁极化场和易磁化轴的组合效应，表现出两个不同的磁化平衡平衡状态，对应于两个不相互相反的磁化方向。 非均质机械应力足够强，以引起两种不同状态之间的切换。

公开(公告)号：EP2469713A2

公开(公告)日：2012-06-27

申请号：EP12160348.4

申请日：2008-03-31

申请人： Qualcomm Incorporated

发明人： Chua-Eoan, Lew G. ,  Norwak, Matthew Michael ,  Kang, Seung H.

IPC分类号： H03K19/177 ,  G11C11/16

CPC分类号： H03K19/17748 ,  G11C11/161 ,  G11C11/165 ,  H03K19/17736 ,  H03K19/1778

摘要： Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.

摘要翻译： 公开了使用旋转转矩磁阻随机存取存储器（STT-MRAM）技术的软件可编程逻辑的系统，电路和方法。 磁隧道结（MTJ）存储元件可以形成输入平面和输出平面。 输入平面和输出平面可以耦合在一起，形成允许实现逻辑功能的复杂阵列。