公开(公告)号：EP3938890A1

公开(公告)日：2022-01-19

申请号：EP20718909.3

申请日：2020-03-14

申请人： Intel Corporation

发明人： APPU, Abhishek ,  MAIYURAN, Subramaniam ,  MACPHERSON, Mike ,  FU, Fangwen ,  CHEN, Jiasheng ,  GEORGE, Varghese ,  RANGANATHAN, Vasanth ,  GARG, Ashutosh ,  RAY, Joydeep

IPC分类号： G06F9/30 ,  G06F9/38

公开(公告)号：EP4155900A1

公开(公告)日：2023-03-29

申请号：EP22184044.0

申请日：2022-07-11

申请人： INTEL Corporation

发明人： CHEN, Jiasheng ,  RHEE, Changwon ,  GANAPATHY, Sabareesh ,  HENRY, Gregory ,  FU, Fangwen

IPC分类号： G06F7/544 ,  G06F7/483

摘要： Emulating floating point calculation using lower precision format calculations is described. An example of a processor includes a floating point unit (FPU) to provide a native floating point operation in a first precision format; and systolic array hardware including multiple data processing units, wherein the processor is to receive data for performance of a matrix multiplication operation in the first precision format; enable an emulated floating point multiplication operation using one or more values with a second precision format, the second precision format having a lower precision than the first precision format, the emulated floating point multiplication including operation of the systolic array hardware; and generate an emulated result for the matrix multiplication operation

公开(公告)号：EP3396958A1

公开(公告)日：2018-10-31

申请号：EP18167132.2

申请日：2018-04-12

申请人： INTEL Corporation

发明人： BOYCE, Jill M. ,  ROWE, Keith W. ,  HOLLAND, James M. ,  FU, Fangwen ,  YEDIDI, Satya N. ,  MOHAN, Sumit

IPC分类号： H04N19/30 ,  G06T15/00 ,  H04N19/42 ,  H04N19/27

CPC分类号： G06T9/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/005 ,  G06T19/006 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2215/16 ,  H04N19/27 ,  H04N19/30 ,  H04N19/42

摘要： A system includes a camera to capture real world content and a semiconductor package apparatus. The semiconductor package apparatus includes a substrate and logic. The logic includes a graphics pipeline to generate rendered content, a base layer encoder to encode real world content into a base layer and a first layer encoder to encode rendered content into a first non-base layer, a multiplexer to interleave the base layer with the first non-base layer to obtain a single output signal having mixed reality content, and a transmitter to transmit the single output signal. The system further includes a second layer encoder to encode map data into a second non-base layer. The multiplexer to interleave the second non-base layer with the first non-base layer and the base layer. The first and second layer encoders encode the rendered content and the map data into overlay auxiliary pictures.

公开(公告)号：EP4113994A3

公开(公告)日：2023-04-05

申请号：EP22191906.1

申请日：2018-03-29

申请人： INTEL Corporation

发明人： BOYCE, Jill M. ,  LEE, Sang-Hee ,  APPU, Abhishek R. ,  KAO, Wen-Fu ,  RAY, Joydeep ,  PENG, Ya-Ti ,  ROWE, Keith W. ,  FU, Fangwen ,  YEDIDI, Satya N. ,  MOHAN, Sumit ,  HOLLAND, James M.

IPC分类号： H04N19/105

摘要： An embodiment of an electronic processing system may include a region identifier to identify a region of interest in a 2D frame which corresponds to a projection of a 360 video space, and a prioritizer communicatively coupled to the region identifier to prioritize transmission for a packet of the 2D frame based on the identified region of interest. Other embodiments are disclosed and claimed.

公开(公告)号：EP3392737A2

公开(公告)日：2018-10-24

申请号：EP18167862.4

申请日：2018-04-17

申请人： INTEL Corporation

发明人： APPU, Abhishek R. ,  BARAN, Stanley J. ,  LEE, Sang-Hee ,  MOHAMMED, Atthar H. ,  OH, Jong Dae ,  CHAN, Hiu-Fai R. ,  BOYCE, Jill M. ,  FU, Fangwen ,  YEDIDI, Satya N. ,  MOHAN, Sumit ,  HOLLAND, James M. ,  ROWE, Keith W. ,  KOKER, Altug

IPC分类号： G06F1/32

CPC分类号： G06T1/20 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3265 ,  G06T1/60 ,  G06T2200/16 ,  G06T2210/52 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/0407 ,  Y02D10/153 ,  Y02D10/174

摘要： An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：EP4359967A1

公开(公告)日：2024-05-01

申请号：EP22717046.1

申请日：2022-03-15

申请人： Intel Corporation

发明人： PARRA, Jorge ,  FU, Fangwen ,  MAIYURAN, Subramaniam ,  GEORGE, Varghese ,  MACPHERSON, Mike ,  PAL, Supratim ,  GURRAM, Chandra ,  GANAPATHY, Sabareesh ,  AVANCHA, Sasikanth ,  VOOTURI, Dharma Teja ,  MELLEMPUDI, Naveen ,  DAS, Dipankar

IPC分类号： G06F17/16 ,  G06F9/00

CPC分类号： G06F17/16 ,  G06F15/8046 ,  G06F9/3001 ,  G06F9/30036

公开(公告)号：EP3392737A3

公开(公告)日：2018-11-28

申请号：EP18167862.4

申请日：2018-04-17

申请人： INTEL Corporation

发明人： APPU, Abhishek R. ,  BARAN, Stanley J. ,  LEE, Sang-Hee ,  MOHAMMED, Atthar H. ,  OH, Jong Dae ,  CHAN, Hiu-Fai R. ,  BOYCE, Jill M. ,  FU, Fangwen ,  YEDIDI, Satya N. ,  MOHAN, Sumit ,  HOLLAND, James M. ,  ROWE, Keith W. ,  KOKER, Altug

IPC分类号： G06F1/32

CPC分类号： G06T1/20 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3265 ,  G06T1/60 ,  G06T2200/16 ,  G06T2210/52 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/0407 ,  Y02D10/153 ,  Y02D10/174

摘要： An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：EP3383041A2

公开(公告)日：2018-10-03

申请号：EP18165263.7

申请日：2018-03-29

申请人： INTEL Corporation

发明人： BOYCE, Jill M. ,  LEE, Sang-Hee ,  APPU, Abhishek R. ,  KAO, Wen-Fu ,  RAY, Joydeep ,  PENG, Ya-Ti ,  ROWE, Keith W. ,  FU, Fangwen ,  YEDIDI, Satya N. ,  MOHAN, Sumit ,  HOLLAND, James M.

IPC分类号： H04N19/105 ,  H04N19/52 ,  H04N19/176 ,  H04N19/593

CPC分类号： H04N19/593 ,  G03B37/04 ,  G06T11/003 ,  H04N19/105 ,  H04N19/176 ,  H04N19/52 ,  H04N19/597

摘要： An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.

公开(公告)号：EP2786576A1

公开(公告)日：2014-10-08

申请号：EP11876665.8

申请日：2011-12-01

申请人： Intel Corporation

发明人： LEE, Sang-Hee ,  FU, Fangwen ,  LEI, Zhijun

IPC分类号： H04N7/32 ,  H04N7/26 ,  H04N7/36

CPC分类号： H04N19/51 ,  H04N19/132 ,  H04N19/184 ,  H04N19/30 ,  H04N19/42 ,  H04N19/43 ,  H04N19/463

摘要： Systems, apparatus and methods are described including determining a first value by reducing a bit-length of a reference pixel value and adding a first predetermined value to the result and determining a second value by subtracting a residual pixel value from a current pixel value to generate a difference value, reducing a bit-length of the difference value and adding the first predetermined value to the result. The range of the second value may then be clipped by setting the second value to zero when the second value is equal to or less than a second predetermined value and setting the second value to a third predetermined value when the second value is equal to or greater than a fourth predetermined value. The first value and the second value may then be used for inter-layer residual prediction in Scalable Video Coding (SVC) systems.

公开(公告)号：EP4359919A1

公开(公告)日：2024-05-01

申请号：EP22714700.6

申请日：2022-03-16

申请人： Intel Corporation

发明人： PARRA, Jorge ,  CHEN, Jiasheng ,  PAL, Supratim ,  FU, Fangwen ,  GANAPATHY, Sabareesh ,  GURRAM, Chandra ,  MEI, Chunhui ,  QI, Yue

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F17/16 ,  G06F15/80

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893 ,  G06F9/3828 ,  G06F17/16 ,  G06F15/8046