摘要:
An apparatus is described. The apparatus includes a semiconductor chip package. The semiconductor chip package includes an SOC. The SOC has a memory controller. The semiconductor chip package includes an interface to an external memory. The semiconductor chip package includes a memory side cache. The memory side cache is composed of eDRAM and is coupled between the memory controller and the interface to the external memory. The eDRAM is to cache more frequently used items of the external memory. The semiconductor chip package has an out-of-order interface between the memory controller and the memory side cache.
摘要:
Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links. The communication links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
摘要:
A microcontroller, processor, and/or software (SW) monitors a battery degradation indicator such as battery State-Of-Health (SOH), impedance or other attributes, and calculates battery degradation rate and regulates burst power, battery charging speed and/or battery charging limit to meet users' expectation of battery service life. The microcontroller, processor, and/or SW increases the burst power, battery charging speed and/or battery charging limit when 1/SOH or impedance change rate (or related parameter) is smaller than expected and there is more longevity budget than expected. In another example, the microcontroller, processor, and/or SW decreases the burst power, battery charging speed and/or battery charging limit when 1/SOH or impedance change rate (or related parameter) is greater than expected and there is less longevity budget than expected.