A METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT

    公开(公告)号:EP3719659A1

    公开(公告)日:2020-10-07

    申请号:EP20175936.2

    申请日:2013-10-30

    申请人: INTEL Corporation

    IPC分类号: G06F13/38

    摘要: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.