公开(公告)号：EP4155917A1

公开(公告)日：2023-03-29

申请号：EP22191516.8

申请日：2022-08-22

申请人： INTEL Corporation

发明人： BANIK, Subrata ,  REGUPATHY, Rajaram ,  ZIMMER, Vincent ,  MANDELBLAT, Julius

IPC分类号： G06F9/4401 ,  G06F11/30 ,  G06F11/34

摘要： Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

公开(公告)号：EP3979115A1

公开(公告)日：2022-04-06

申请号：EP21193481.5

申请日：2021-08-27

申请人： Intel Corporation

发明人： ZIMMER, Vincent ,  BANIK, Subrata ,  REGUPATHY, Rajaram

IPC分类号： G06F21/57 ,  G06F9/4401

摘要： Systems, apparatuses and methods may provide for technology that initializes static random access memory (SRAM) of a processor in response to a reset of the processor, allocates the SRAM to one or more security enforcement operations, and triggers a multi-threaded execution of the one or more security enforcement operations before completion of a basic input output system (BIOS) phase. In one example, the multi-threaded execution is triggered independently of a dynamic RAM (DRAM) initialization.

公开(公告)号：EP4359923A1

公开(公告)日：2024-05-01

申请号：EP21940006.6

申请日：2021-12-24

申请人： Intel Corporation

发明人： ZIMMER, Vincent ,  JAIN, Nilesh ,  POORNACHANDRAN, Rajesh ,  DAVARE, Abhijit ,  BALASUBRAMANIAN, Kaushik ,  LACEWELL, Chaunte ,  PUTTANNAIAH, Karan ,  FANG, Jiahao ,  BANIK, Subrata ,  REGUPATHY, Rajaram ,  THOMAS, Salil Mathachan

IPC分类号： G06F9/445 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06F9/4403 ,  G06N3/0464 ,  G06N3/0455 ,  G06N3/092 ,  G06N3/0985 ,  G06N3/044 ,  G06N5/022

公开(公告)号：EP3979072A1

公开(公告)日：2022-04-06

申请号：EP21183690.3

申请日：2021-07-05

申请人： INTEL Corporation

发明人： ZIMMER, Vincent ,  POOVALUR RANGARAJAN, Ravi ,  BANIK, Subrata ,  REGUPATHY, Rajaram

IPC分类号： G06F8/65 ,  G06F9/4401 ,  G06F9/50 ,  G06F11/34

摘要： Systems, apparatuses and methods may provide for technology that identifies, during a first boot process, whether at least one task associated with at least one software program is set to occur in a single-threaded process or a multithreaded process, in response to the at least one task being set to occur in the multithreaded process, executing the at least one task in the multithreaded process during the first boot process, and in response to the at least one task being set to occur in the single-threaded process, executing the at least one task in the single-threaded process during the first boot process.

公开(公告)号：EP3971713A1

公开(公告)日：2022-03-23

申请号：EP21191559.0

申请日：2021-08-16

申请人： INTEL Corporation

发明人： BANIK, Subrata ,  VAGHELA, Maulik ,  REGUPATHY, Rajaram ,  ZIMMER, Vincent ,  AZAM, Asad

IPC分类号： G06F9/4401 ,  G06F12/0811 ,  G06F12/084 ,  G06F3/14

摘要： Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

公开(公告)号：EP3869348A1

公开(公告)日：2021-08-25

申请号：EP20211463.3

申请日：2020-12-03

申请人： INTEL Corporation

发明人： ISMAIL, Abdul ,  EWERT, Peter ,  DAS, Sajal Kumar ,  K V, Abhilash ,  REGUPATHY, Rajaram

IPC分类号： G06F13/42

摘要： Systems, apparatuses and methods may provide for technology that collects state data from a plurality of input/output (IO) drivers, wherein each of the plurality of IO drivers is to tunnel traffic through a shared physical interface in accordance with a different protocol. The technology also determines, based on the state data, a bandwidth allocation of the shared physical interface among the plurality of IO drivers, and automatically initiates, based on the bandwidth allocation, a state change of a processor coupled to the shared physical interface

公开(公告)号：EP4439323A1

公开(公告)日：2024-10-02

申请号：EP23213816.4

申请日：2023-12-01

申请人： Intel Corporation

发明人： REGUPATHY, Rajaram ,  ROZIC, Reuven ,  BERCHANSKIY, Dmitriy ,  BAILUR, Nirmala ,  PANSE, Vrukesh V. ,  GOPAL, Saranya

IPC分类号： G06F13/42

CPC分类号： G06F13/4295 ,  G06F2213/004220130101 ,  G06F2213/006220130101

摘要： A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

公开(公告)号：EP3905005A1

公开(公告)日：2021-11-03

申请号：EP20211534.1

申请日：2020-12-03

申请人： INTEL Corporation

发明人： EWERT, Peter ,  SOWMYA, V ,  BANIK, Subrata ,  P, Vagdevi ,  REGUPATHY, Rajaram

IPC分类号： G06F1/3212 ,  H02J7/00 ,  H02J9/00 ,  G06F11/14

摘要： Systems, apparatuses and methods may provide for technology that initiates a boot of a computing system containing an embedded controller while the computing system is in a low power mode, conducts a verification that code to perform the boot is uncorrupted, and negotiates an increased power delivery with a source device connected to the computing system if the verification is successful.