公开(公告)号：EP4064334A1

公开(公告)日：2022-09-28

申请号：EP22157639.0

申请日：2022-02-20

申请人： INTEL Corporation

发明人： LILAK, Aaron D. ,  WEBER, Cory ,  CEA, Stephen M. ,  PIPES, Leonard C. ,  HWANGBO, Seahee ,  MEHANDRU, Rishabh ,  KEYS, Patrick ,  YAUNG, Jack ,  OU, Tzu-Min

IPC分类号： H01L21/8238 ,  H01L29/66

摘要： Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm 3 . A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：EP4156282A1

公开(公告)日：2023-03-29

申请号：EP22190044.2

申请日：2022-08-11

申请人： Intel Corporation

发明人： GHANI, Tahir ,  MURTHY, Anand S. ,  CEA, Stephen M. ,  WEBER, Cory ,  MEHANDRU, Rishabh ,  LILAK, Aaron D. ,  KEYS, Patrick ,  GUHA, Biswajeet ,  OMAR, Sabih ,  HSU, William ,  HAN, Chang Wan ,  HASAN, Mohammad ,  PARK, Kihoon

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00

摘要： Gate-all-around integrated circuit structures having a doped subfin (292, 296, 297), and methods of fabricating gate-all-around integrated circuit structures having a doped subfin (292, 296, 297), are described. For example, an integrated circuit structure includes a subfin structure (292, 296, 297) having dopants with a concentration of more than 1E18 per cube centimetre. A vertical arrangement of horizontal semiconductor nanowires (299) is over the subfin structure. A gate stack (298) is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires. The sub-fin doping may be achieved by counter-doping.

公开(公告)号：EP3647262A1

公开(公告)日：2020-05-06

申请号：EP19183069.4

申请日：2019-06-27

申请人： INTEL Corporation

发明人： GLASS, Glenn ,  MURTHY, Anand ,  GUHA, Biswajeet ,  CRUM, Dax ,  KEYS, Patrick ,  GHANI, Tahir ,  GHOSE, Susmita ,  COOK JR, Ted

IPC分类号： B82Y10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423

摘要： Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers (250) are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires (206) above a fin. The fin includes a dopant diffusion blocking layer (250) on a first semiconductor layer (202), and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack (226, 228) is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure (222, 224) is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure (222, 224) is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：EP4156294A1

公开(公告)日：2023-03-29

申请号：EP22191315.5

申请日：2022-08-19

申请人： Intel Corporation

发明人： CEA, Stephen ,  WEBER, Cory ,  MEHANDRU, Rishabh ,  LILAK, Aaron ,  KEYS, Patrick

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00

摘要： Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

公开(公告)号：EP4109557A1

公开(公告)日：2022-12-28

申请号：EP22179997.6

申请日：2022-06-20

申请人： INTEL Corporation

发明人： MEHANDRU, Rishabh ,  CEA, Stephen ,  GHANI, Tahir ,  KEYS, Patrick ,  LILAK, Aaron D. ,  MURTHY, Anand ,  WEBER, Cory

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  B82Y10/00

摘要： Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.