公开(公告)号：EP4203057A1

公开(公告)日：2023-06-28

申请号：EP22201131.4

申请日：2022-10-12

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  KUMAR, Nitesh ,  SHAH, Rushabh ,  MURTHY, Anand S. ,  PATEL, Pratik ,  GHANI, Tahir ,  MEYER, Tricia ,  BOMBERGER, Cory ,  GLASS, Glenn A. ,  CEA, Stephen M. ,  JAHAGIRDAR, Anant H.

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/10

摘要： Gate-all-around integrated circuit structures having source or drain structures (124) with substrate connection portions (124A), and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires (108). A gate stack (126, 128) is over the vertical arrangements of nanowires (108) and completely surrounding each nanowire (108). A first epitaxial source or drain structure (124) is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure (124) is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion (124B) and a lower epitaxial extension portion (124A), the latter being recessed into the substrate (102).

公开(公告)号：EP3588576A1

公开(公告)日：2020-01-01

申请号：EP19176633.6

申请日：2019-05-24

申请人： INTEL Corporation

发明人： CRUM, Dax M. ,  GUHA, Biswajeet ,  HSU, William ,  CEA, Stephen M. ,  GHANI, Tahir

IPC分类号： H01L29/417 ,  H01L29/66

摘要： Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer (340) are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material (360), such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal (380) to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures (320) on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

公开(公告)号：EP2517254A2

公开(公告)日：2012-10-31

申请号：EP10843439.0

申请日：2010-12-02

申请人： Intel Corporation

发明人： CEA, Stephen M. ,  MEHANDRU, Rishabh ,  SHIFREN, Lucian ,  KUHN, Kelin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858

摘要： A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface.

公开(公告)号：EP4345879A1

公开(公告)日：2024-04-03

申请号：EP23193407.6

申请日：2023-08-25

申请人： INTEL Corporation

发明人： GULER, Leonard P. ,  YEMENICIOGLU, Sukru ,  HARAN, Mohit K. ,  CEA, Stephen M. ,  WALLACE, Charles H. ,  GHANI, Tahir ,  LIU, Shengsi ,  ACHARYA, Saurabh ,  O'BRIEN, Thomas ,  KHANDELWAL, Nidhi ,  CONTE, Marie ,  LUTHRA, Prabhjot

IPC分类号： H01L21/8234 ,  H01L29/06

摘要： Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：EP4156281A1

公开(公告)日：2023-03-29

申请号：EP22185002.7

申请日：2022-07-14

申请人： Intel Corporation

发明人： NANDI, Debaleena ,  KOBRINSKY, Mauro J. ,  DEWEY, Gilbert ,  CHOI, Chi-hing ,  Kennel, Harold W. ,  KRIST, Brian J. ,  ALIYARUKUNJU, Ashkar ,  BOMBERGER, Cory ,  SHAH, Rushabh ,  MEHANDRU, Rishabh ,  CEA, Stephen M. ,  MUNASINGHE, Chanaka ,  MURHTY, Anand ,  GHANI, Tahir

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/423 ,  H01L21/336 ,  H01L29/775 ,  H01L27/092 ,  B82Y10/00

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.

公开(公告)号：EP3588546A1

公开(公告)日：2020-01-01

申请号：EP19176628.6

申请日：2019-05-24

申请人： INTEL Corporation

发明人： LILAK, Aaron D. ,  MEHANDRU, Rishabh ,  PHAN, Anh ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  CEA, Stephen M. ,  HASAN, Sayed ,  FOLEY, Kerryann M. ,  MORROW, Patrick ,  LANDON, Colin D. ,  MANNEBACH, Ehren

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66

摘要： Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：EP2920815A1

公开(公告)日：2015-09-23

申请号：EP13854345.9

申请日：2013-06-12

申请人： Intel Corporation

发明人： KOTLYAR, Roza ,  CEA, Stephen M. ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin ,  AVCI, Uygar E. ,  RIOS, Rafael ,  CHAUDHRY, Anurag ,  LINTON, JR., Thomas D. ,  YOUNG, Ian A. ,  KUHN, Kelin J.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：EP4064334A1

公开(公告)日：2022-09-28

申请号：EP22157639.0

申请日：2022-02-20

申请人： INTEL Corporation

发明人： LILAK, Aaron D. ,  WEBER, Cory ,  CEA, Stephen M. ,  PIPES, Leonard C. ,  HWANGBO, Seahee ,  MEHANDRU, Rishabh ,  KEYS, Patrick ,  YAUNG, Jack ,  OU, Tzu-Min

IPC分类号： H01L21/8238 ,  H01L29/66

摘要： Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm 3 . A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：EP4020590A1

公开(公告)日：2022-06-29

申请号：EP21198785.4

申请日：2021-09-24

申请人： Intel Corporation

发明人： KAVALIEROS, Jack T. ,  RACHMADY, Willy ,  CHOUKSEY, Siddharth ,  CEA, Stephen M. ,  AGRAWAL, Ashish

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  B82Y10/00

摘要： Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：EP3998639A1

公开(公告)日：2022-05-18

申请号：EP21210432.7

申请日：2013-06-12

申请人： INTEL Corporation

发明人： CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/10

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the builtin stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric / semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric / semiconductor interface.