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    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS
    2.
    发明公开
    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS 审中-公开

    公开(公告)号：EP3675158A3

    公开(公告)日：2020-08-05

    申请号：EP19209555.2

    申请日：2019-11-15

    申请人： Intel Corporation

    发明人： HUANG, Cheng-Ying ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  LILAK, Aaron ,  JUN, Kimin ,  MUELLER, Brennen ,  MANNEBACH, Ehren ,  PHAN, Anh ,  MORROW, Patrick ,  YOO, Hui Jae ,  KAVALIEROS, Jack

    IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

    摘要： Embodiments herein describe techniques for a semiconductor device including a first transistor (120) stacked above and self-aligned with a second transistor (110), where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode (129), a first channel layer (123) including a first channel material and separated from the first gate electrode by a first gate dielectric layer (128), and a first source electrode (125) coupled to the first channel layer. The second transistor includes a second gate electrode (109), a second channel layer (103) including a second channel material and separated from the second gate electrode by a second gate dielectric layer (108), and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer (115). Other embodiments may be described and/or claimed.

    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING
    4.
    发明公开
    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING 审中-公开

    公开(公告)号：EP3712937A1

    公开(公告)日：2020-09-23

    申请号：EP20153079.7

    申请日：2020-01-22

    申请人： INTEL Corporation

    发明人： MANNEBACH, Ehren ,  LILAK, Aaron ,  MEHANDRU, Rishabh ,  YOO, Hui Jae ,  MORROW, Patrick ,  LIN, Kevin

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/84 ,  H01L23/31 ,  H01L27/12 ,  H01L29/49

    摘要： Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.