公开(公告)号：EP4020555A1

公开(公告)日：2022-06-29

申请号：EP21195027.4

申请日：2021-09-06

申请人： INTEL Corporation

发明人： ALAAN, Urusa ,  SHARMA, Abhishek ,  KUO, Charles ,  ORR, Benjamin ,  THOMSON, Nicholas

IPC分类号： H01L27/02 ,  H01L29/872 ,  H01L29/24

摘要： Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

公开(公告)号：EP3563432A1

公开(公告)日：2019-11-06

申请号：EP16925528.8

申请日：2016-12-28

申请人： INTEL Corporation

发明人： BROCKMAN, Justin ,  WIEGAND, Christopher ,  RAHMAN, MD Tofizur ,  OUELETTE, Daniel ,  SMITH, Angeline ,  ALZATE VINASCO, Juan ,  KUO, Charles ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  GOLONZKA, Oleg ,  GHANI, Tahir

IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L43/10

公开(公告)号：EP2831880B1

公开(公告)日：2017-03-15

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/16

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

公开(公告)号：EP2831880A1

公开(公告)日：2015-02-04

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/15

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.