公开(公告)号：EP2831880A4

公开(公告)日：2015-12-09

申请号：EP12872781

申请日：2012-03-25

申请人： INTEL CORP

发明人： RAYCHOWDHURY ARIJIT ,  KENCKE DAVID ,  DOYLE BRIAN ,  KUO CHARLES ,  TSCHANZ JAMES ,  HAMZAOGLU FATIH ,  WANG YIH ,  GOLIZADEH MOJARAD ROKSANA

IPC分类号： G11C11/16

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

公开(公告)号：EP3254288A1

公开(公告)日：2017-12-13

申请号：EP16746935.2

申请日：2016-01-11

申请人： Micron Technology, Inc.

发明人： KARDA, Kamal, M. ,  MILOJEVIC, Marko ,  WELLS, David, H. ,  GEALY, F., Daniel

IPC分类号： G11C11/21 ,  G11C11/34

CPC分类号： H01L45/126 ,  G11C5/12 ,  G11C11/221 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally activated conduction activation energy of 0.5 eV to 3.0 eV. A second current path extends from the one electrode to the other and is circuit-parallel the first current path. The second current path exhibits a minimum 100-times increase in electrical conductivity for increasing temperature within a temperature range of no more than 50° C. between 300° C. and 800° C. and exhibits a minimum 100-times decrease in electrical conductivity for decreasing temperature within the 50° C. temperature range. Other embodiments are disclosed.

公开(公告)号：EP2831880B1

公开(公告)日：2017-03-15

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/16

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

公开(公告)号：EP2831880A1

公开(公告)日：2015-02-04

申请号：EP12872781.5

申请日：2012-03-25

申请人： Intel Corporation

发明人： RAYCHOWDHURY, Arijit ,  KENCKE, David ,  DOYLE, Brian ,  KUO, Charles ,  TSCHANZ, James ,  HAMZAOGLU, Fatih ,  WANG, Yih ,  GOLIZADEH MOJARAD, Roksana

IPC分类号： G11C11/15

CPC分类号： G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

公开(公告)号：EP1196951B1

公开(公告)日：2013-04-03

申请号：EP00954331.5

申请日：2000-07-13

申请人： Qimonda AG

发明人： WÖRZ, Andreas ,  GOTTLIEB, Alfred ,  RÖMER, Bernd

IPC分类号： H01L25/10

CPC分类号： G11C5/06 ,  G11C5/12 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1196951A1

公开(公告)日：2002-04-17

申请号：EP00954331.5

申请日：2000-07-13

申请人： Infineon Technologies AG

发明人： WÖRZ, Andreas ,  GOTTLIEB, Alfred ,  RÖMER, Bernd

IPC分类号： H01L25/10

CPC分类号： G11C5/06 ,  G11C5/12 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to an arrangement of at least two stacked TSOP memory chip housings, each comprising at least one memory chip with several pins arranged inside the TSOP memory chip housing, whereby said pins are guided through the respective TSOP memory chip housing and connected, via a wiring arrangement, to pins which are guided through a directly adjacent TSOP memory chip housing. In order to create a housing stack using an automated assembly process which is as inexpensive as possible and to enable said stack to be produced in the easiest possible manner, the wiring arrangement is provided in the form of leadfames which are respectively arranged between or arranged laterally between the individual TSOP memory chip housings.