公开(公告)号：EP3519943A1

公开(公告)日：2019-08-07

申请号：EP17856975.2

申请日：2017-08-09

申请人： Intel Corporation

发明人： DUBTSOV, Roman S. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  GIRKAR, Milind ,  OULD-AHMED-VALL, Elmoustapha

IPC分类号： G06F9/30 ,  G06F7/48

公开(公告)号：EP3602279A1

公开(公告)日：2020-02-05

申请号：EP17901997.1

申请日：2017-07-01

申请人： Intel Corporation

发明人： VALENTINE, Robert ,  BAUM, Dan ,  SPERBER, Zeev ,  CORBAL, Jesus ,  OULD-AHMED-VALL, Elmoustapha ,  TOLL, Bret L. ,  CHARNEY, Mark J. ,  ZIV, Barukh ,  HEINECKE, Alexander ,  GIRKAR, Milind ,  RUBANOVICH, Simon

IPC分类号： G06F9/30

公开(公告)号：EP1668500B1

公开(公告)日：2010-04-21

申请号：EP04785288.4

申请日：2004-09-29

申请人： Intel Corporation

发明人： HOFLEHNER, Gerolf ,  LIAO, Shih-Wei ,  TIAN, Xinmin ,  WANG, Hong ,  LAVERY, Daniel ,  WANG, Perry ,  KIM, Dongkeun ,  GIRKAR, Milind ,  SHEN, John

IPC分类号： G06F9/45

CPC分类号： G06F8/441

公开(公告)号：EP1668500A1

公开(公告)日：2006-06-14

申请号：EP04785288.4

申请日：2004-09-29

申请人： INTEL CORPORATION

发明人： HOFLEHNER, Gerolf ,  LIAO, Shih-Wei ,  TIAN, Xinmin ,  WANG, Hong ,  LAVERY, Daniel ,  WANG, Perry ,  KIM, Dongkeun ,  GIRKAR, Milind ,  SHEN, John

IPC分类号： G06F9/45

CPC分类号： G06F8/441

摘要： Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

公开(公告)号：EP2494454A1

公开(公告)日：2012-09-05

申请号：EP09850970.6

申请日：2009-10-30

申请人： Intel Corporation

发明人： YAN, Shoumeng ,  ZHOU, Xiaocheng ,  GAO, Ying ,  RAJAGOPALAN, Mohan ,  DEODHAR, Rajiv ,  PUTZOLU, David ,  NELSON, Clark ,  GIRKAR, Milind ,  GEVA, Robert ,  CHEN, Tiger ,  LUO, Sai ,  JUNKINS, Stephen ,  SAHA, Bratin ,  PUTZOLU, David ,  NARAYANASWAMY, Ravi ,  LUO, Sai ,  XI, Patrick

IPC分类号： G06F15/16 ,  G06F9/28 ,  G06F15/167

CPC分类号： G06F9/544 ,  G06F9/547

摘要： A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU, for example. The GPU may be coupled to a GPU compiler and a GPU linker/loader and the CPU may be coupled to a CPU compiler and a CPU linker/loader. The user may create a shared object in an object oriented language and the shared object may include virtual functions. The shared object may be fine grain partitioned between the heterogeneous processors. The GPU compiler may allocate the shared object to the CPU and may create a first and a second enabling path to allow the GPU to invoke virtual functions of the shared object. Thus, the shared object that may include virtual functions may be shared seamlessly between the CPU and the GPU.

公开(公告)号：EP1678610A2

公开(公告)日：2006-07-12

申请号：EP04789368.0

申请日：2004-09-29

申请人： INTEL CORPORATION

发明人： TIAN, Xinmin ,  LIAO, Shih-Wei ,  WANG, Hong ,  GIRKAR, Milind ,  SHEN, John ,  WANG, Perry ,  HAAB, Grant ,  HOFLEHNER, Gerolf ,  LAVERY, Daniel ,  SAITO, Hideki ,  SHAH, Sanjiv ,  KIM, Dongkeun

IPC分类号： G06F9/45

CPC分类号： G06F9/3851 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/4843 ,  G06F9/52

摘要： Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

公开(公告)号：EP2097808A1

公开(公告)日：2009-09-09

申请号：EP07869459.3

申请日：2007-12-18

申请人： Intel Corporation

发明人： LUEH, Guei-Yuan ,  JIANG, Hong ,  RIFFEL, Andrew T. ,  ZHENG, Bixia ,  LIM, Chu-Cheow ,  GIRKAR, Milind ,  SEHR, David C. ,  PIAZZA, Thomas A.

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F8/4434 ,  G06F8/447 ,  G06F9/30036 ,  G06F9/30156 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3853

摘要： In some embodiments, a data structure may be received in a first processing system. The data structure may represent a plurality of instructions for a second processing system. For at least one instruction of the plurality of instructions, a determination may be made as to whether the instruction can be replaced by a compact instruction for the second processing system. A compact instruction may be generated if the instruction can be replaced by a compact instruction. In some embodiments, an instruction may be received in a processing system. A determination may be made as to whether the instruction is a compact instruction. A decompacted instruction may be generated if the instruction is a compact instruction.

公开(公告)号：EP1949227A1

公开(公告)日：2008-07-30

申请号：EP06825144.6

申请日：2006-08-26

申请人： Intel Corporation

发明人： TIAN, Xinmin ,  GIRKAR, Milind ,  SHER, David ,  GROVE, Richard ,  LI, Wei ,  WANG, Hong ,  NEWBURN, Chris ,  WANG, Perry ,  SHEN, John

IPC分类号： G06F9/45

CPC分类号： G06F8/45

摘要： Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.

公开(公告)号：EP1668502A2

公开(公告)日：2006-06-14

申请号：EP04789475.3

申请日：2004-09-30

申请人： INTEL CORPORATION

发明人： LIAO, Shih-wei ,  TIAN, Xinmin ,  HOFLEHNER, Gerolf, F. ,  WANG, Hong ,  LAVERY, Daniel, M. ,  WANG, Perry ,  KIM, Dongkeun ,  GIRKAR, Milind ,  SHEN, John, P.

IPC分类号： G06F9/45

CPC分类号： G06F9/3842 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/3851

摘要： Methods and apparatuses for compiler- created helper thread for multi­threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.