公开(公告)号：EP4293724A1

公开(公告)日：2023-12-20

申请号：EP23172203.4

申请日：2023-05-09

申请人： INTEL Corporation

发明人： GALATAGE, Rohit ,  RACHMADY, Willy ,  RAFIQUE, Subrina ,  KUMAR, Nitesh ,  HUANG, Cheng-Ying ,  WIEDEMER, Jami A. ,  THOMAS, Nicole K. ,  QAYYUM, Munzarin F. ,  MORROW, Patrick ,  RADOSAVLJEVIC, Marko ,  KOBRINSKY, Mauro J.

IPC分类号： H01L29/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00

摘要： An integrated circuit structure includes a device including a source region (104a, 105a, 133a), a drain region (104b, 105b, 133b), a body (103) laterally between the source and drain regions, and a source contact (118a, 135) coupled to the source region. The source region includes a first region (105a), and a second region (133a) compositionally different from and above the first region. The source contact (118a, 135) extends through, and is in direct contact with, the second region (133a) and extends within and is in direct contact with the first region (105a). In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.

公开(公告)号：EP4199062A1

公开(公告)日：2023-06-21

申请号：EP22206578.1

申请日：2022-11-10

申请人： INTEL Corporation

发明人： RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  AGRAWAL, Ashish ,  MORROW, Patrick ,  SUNG, Seung Hoon ,  HUANG, Cheng-Ying ,  THOMAS, Nicole ,  HARATIPOUR, Nazila

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L27/092 ,  H01L21/8238

摘要： Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel and the p-channel, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact is formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

公开(公告)号：EP3886177A1

公开(公告)日：2021-09-29

申请号：EP20216329.1

申请日：2020-12-22

申请人： INTEL Corporation

发明人： RACHMADY, Willy ,  MEHANDRU, Rishabh ,  LILAK, Aaron ,  MISHRA, Varun ,  WEBER, Cory

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/336 ,  H01L29/08

摘要： Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：EP3732721A1

公开(公告)日：2020-11-04

申请号：EP17935901.3

申请日：2017-12-27

申请人： Intel Corporation

发明人： LILAK, Aaron ,  MEHANDRU, Rishabh ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  PHAN, Anh

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

公开(公告)号：EP3688813A1

公开(公告)日：2020-08-05

申请号：EP17927294.3

申请日：2017-09-28

申请人： INTEL Corporation

发明人： LE, Van H. ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  RACHMADY, Willy ,  PILLARISETTY, Ravi ,  SHARMA, Abhishek ,  DEWEY, Gilbert ,  DASGUPTA, Sansaptak

IPC分类号： H01L29/778 ,  H01L29/66

公开(公告)号：EP3685443A1

公开(公告)日：2020-07-29

申请号：EP17925227.5

申请日：2017-09-18

申请人： INTEL Corporation

发明人： MAJHI, Prashant ,  RACHMADY, Willy ,  DOYLE, Brian S. ,  SHARMA, Abhishek A. ,  KARPOV, Elijah V. ,  PILLARISETTY, Ravi ,  KAVALIEROS, Jack T.

IPC分类号： H01L29/786

公开(公告)号：EP3629374A3

公开(公告)日：2020-07-22

申请号：EP19183099.1

申请日：2019-06-28

申请人： INTEL Corporation

发明人： SHARMA, Abhishek A. ,  RACHMADY, Willy ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T.

IPC分类号： H01L27/108 ,  H01L27/06

摘要： A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.

公开(公告)号：EP3588546A1

公开(公告)日：2020-01-01

申请号：EP19176628.6

申请日：2019-05-24

申请人： INTEL Corporation

发明人： LILAK, Aaron D. ,  MEHANDRU, Rishabh ,  PHAN, Anh ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  CEA, Stephen M. ,  HASAN, Sayed ,  FOLEY, Kerryann M. ,  MORROW, Patrick ,  LANDON, Colin D. ,  MANNEBACH, Ehren

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66

摘要： Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：EP2517253B1

公开(公告)日：2019-01-23

申请号：EP10843444.0

申请日：2010-12-02

申请人： Intel Corporation

发明人： KAVALIEROS, Jack, T. ,  RACHMADY, Willy ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  GOE, Niti ,  LEE, Yong Ju ,  MAJHI, Prashant ,  TSAI, Wilman ,  DEWEY, Gilbert

IPC分类号： H01L29/778 ,  H01L21/335 ,  H01L21/225 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66 ,  H01L29/20

公开(公告)号：EP3238264A1

公开(公告)日：2017-11-01

申请号：EP14909221.5

申请日：2014-12-23

申请人： Intel Corporation

发明人： RACHMADY, Willy ,  METZ, Matthew V. ,  MOHAPATRA, Chandra S. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia M. ,  GHANI, Tahir ,  GLASS, Glenn A.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/762 ,  H01L27/108 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

摘要： An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.

摘要翻译： 一种包括设置在衬底上的外延子鳍结构，其中，所述子鳍结构的第一部分设置在所述衬底的一部分内，并且所述子鳍结构的第二部分设置为与电介质材料相邻。 鳍式装置结构设置于鳍式结构上，其中鳍式装置结构包括外延材料。 衬垫布置在子鳍状结构的第二部分和电介质材料之间。 这里描述了其他实施例。