公开(公告)号：EP4202980A1

公开(公告)日：2023-06-28

申请号：EP22208162.2

申请日：2022-11-17

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  KUMAR, Nitesh ,  SHAH, Rushabh ,  MURTHY, Anand S. ,  PATEL, Pratik ,  GULER, Leonard P. ,  GHANI, Tahir

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  B82Y10/00

摘要： Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

公开(公告)号：EP4199066A1

公开(公告)日：2023-06-21

申请号：EP22213216.9

申请日：2022-12-13

申请人： INTEL Corporation

发明人： BOUCHE, Guillaume ,  NAVABI-SHIRAZI, Aryan ,  WEI, Andy Chih-Hung ,  KOBRINSKY, Mauro ,  MILLS, Shaun ,  PATEL, Pratik

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. An integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures (268A) are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures (268B) are at ends of the second vertical arrangement of nanowires. A conductive structure (262) is vertically beneath and in contact with one of the first epitaxial source or drain structures (268A).

公开(公告)号：EP4148776A1

公开(公告)日：2023-03-15

申请号：EP22189218.5

申请日：2022-08-08

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  GHANI, Tahir ,  PATEL, Pratik ,  GULER, Leonard ,  ONG, Clifford ,  HARAN, Mohit

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06

摘要： Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device (102) may be a GAA transistor with a first number of semiconductor nanoribbons (112a) while the n-channel device (104) may be a GAA transistor with a second number of semiconductor nanoribbons (112b) that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

公开(公告)号：EP4454019A1

公开(公告)日：2024-10-30

申请号：EP22912230.4

申请日：2022-11-15

申请人： Intel Corporation

发明人： HASAN, Mohammad ,  HARAN, Mohit K. ,  GULER, Leonard P. ,  PATEL, Pratik ,  GHANI, Tahir ,  MURTHY, Anand S. ,  ABD EL QADER, Makram

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

公开(公告)号：EP4300591A1

公开(公告)日：2024-01-03

申请号：EP23173199.3

申请日：2023-05-12

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  ZIGONEANU, Imola ,  DEWEY, Gilbert ,  JAHAGIRDAR, Anant H. ,  KENNEL, Harold W. ,  PATEL, Pratik ,  MURTHY, Anand ,  CHOI, Chi-Hing ,  KOBRINSKY, Mauro J. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm 2 .

公开(公告)号：EP4148804A1

公开(公告)日：2023-03-15

申请号：EP22190217.4

申请日：2022-08-12

申请人： Intel Corporation

发明人： HASAN, Mohammad ,  GHANI, Tahir ,  PATEL, Pratik ,  GULER, Leonard P. ,  HARAN, Mohit ,  ONG, Clifford

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

公开(公告)号：EP3087589A1

公开(公告)日：2016-11-02

申请号：EP13900223.2

申请日：2013-12-27

申请人： Intel Corporation

发明人： PATEL, Pratik ,  LIU, Mark, Y. ,  WIEDEMER, Jami, A. ,  PACKAN, Paul, A.

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

摘要： A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings injunction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

摘要翻译： 一种方法，包括在鳍片的接合区域中形成开口并在基底上延伸; 在开口中引入掺杂的半导体材料; 和热处理掺杂半导体材料。 一种方法，包括在从基板延伸的翅片上形成栅电极; 在所述鳍片的邻近所述栅电极的相对侧上形成开口; 在开口中引入掺杂的半导体材料; 并且热处理足以引起掺杂半导体材料中掺杂剂扩散的掺杂​​半导体材料。 一种装置，包括横跨从基板延伸的翅片的栅电极; 以及半导体材料填充的开口，在栅电极的相邻相对侧的鳍的结区中，其中半导体材料包括掺杂剂。

公开(公告)号：EP4300558A1

公开(公告)日：2024-01-03

申请号：EP23172259.6

申请日：2023-05-09

申请人： INTEL Corporation

发明人： HARAN, Mohit ,  YEMENICIOGLU, Sukru ,  PATEL, Pratik ,  WALLACE, Charles H. ,  GULER, Leonard P. ,  PULS, Conor P. ,  ABD EL QADER, Makram ,  GHANI, Tahir

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535

摘要： Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：EP4203073A1

公开(公告)日：2023-06-28

申请号：EP22209196.9

申请日：2022-11-23

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  CHUNG, Wonil ,  GUHA, Biswajeet ,  MANDAL, Saptarshi ,  PATEL, Pratik ,  GHANI, Tahir ,  CEA, Stephen M. ,  MURTHY, Anand S.

IPC分类号： H01L29/78 ,  H01L29/775

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits (100) utilizing gate plugs (114) to induce compressive channel strain (116). Other embodiments may be described or claimed.

公开(公告)号：EP4156293A1

公开(公告)日：2023-03-29

申请号：EP22189549.3

申请日：2022-08-09

申请人： Intel Corporation

发明人： GHANI, Tahir ,  MURTHY, Anand ,  PATEL, Pratik ,  KEECH, Ryan ,  HASAN, Mohammad ,  RAFIQUE, Subrina ,  GANGULY, Koustav

IPC分类号： H01L29/775 ,  H01L29/08 ,  H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/306 ,  H01L21/20 ,  B82Y10/00

摘要： Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials. In particular a nanosheet FET (1000) is disclosed, with nanosheets (108), gate (1001) and epitaxially grown source/drain materials (106, 107). The width of the source/drain regions is larger than the width of the nanosheets, but not more than one-third.