公开(公告)号：EP1488284A2

公开(公告)日：2004-12-22

申请号：EP03711440.2

申请日：2003-03-06

申请人： INTEL CORPORATION

发明人： SCHENKER, Richard ,  ALLEN, Gary

IPC分类号： G03F1/14 ,  G03F1/00

CPC分类号： G03F1/26 ,  G03F1/32 ,  G03F1/36

摘要： A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature (311 - 314, 373 - 377) or phase shifted low aspect primary features (315, 371, 372) .

公开(公告)号：EP3678170A1

公开(公告)日：2020-07-08

申请号：EP19209319.3

申请日：2019-11-15

申请人： Intel Corporation

发明人： MANNEBACH, Ehren ,  PHAN, Anh ,  LILAK, Aaron ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  HUANG, Cheng-Ying ,  SCHENKER, Richard ,  YOO, Hui Jae ,  MORROW, Patrick

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires comprising oxide nanowires (350A, 350B, 350C). A second vertical arrangement of nanowires above the first vertical arrangement of nanowires comprises active nanowires (314A, 314B, 314C, 314D).

公开(公告)号：EP1488284B1

公开(公告)日：2006-12-20

申请号：EP03711440.2

申请日：2003-03-06

申请人： INTEL CORPORATION

发明人： SCHENKER, Richard ,  ALLEN, Gary

IPC分类号： G03F1/14 ,  G03F1/00

CPC分类号： G03F1/26 ,  G03F1/32 ,  G03F1/36

摘要： A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature (311 - 314, 373 - 377) or phase shifted low aspect primary features (315, 371, 372) .

公开(公告)号：EP4016602A1

公开(公告)日：2022-06-22

申请号：EP21198414.1

申请日：2021-09-23

申请人： INTEL Corporation

发明人： SINGH, Gurpreet ,  HAN, Eungnak ,  CHANDHOK, Manish ,  SCHENKER, Richard ,  GSTREIN, Florian ,  NYHUS, Paul ,  WALLACE, Charles

IPC分类号： H01L21/768 ,  H01L23/532 ,  G03F7/00

摘要： Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

公开(公告)号：EP3796370A1

公开(公告)日：2021-03-24

申请号：EP20181046.2

申请日：2020-06-19

申请人： INTEL Corporation

发明人： SCHENKER, Richard ,  HOURANI, Rami ,  GSTREIN, Florian ,  CHANDHOK, Manish ,  NYHUS, Paul ,  WARD, Curtis ,  WALLACE, Charles ,  GULER, Leonard ,  HARAN, Mohit ,  PATEL, Reken

IPC分类号： H01L21/768

摘要： Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.