公开(公告)号：EP4191655A3

公开(公告)日：2023-08-23

申请号：EP22204391.1

申请日：2022-10-28

申请人： INTEL Corporation

发明人： HUANG, Cheng-Ying ,  MORROW, Patrick ,  VENKATARAMAN, Arunshankar ,  MA, Sean T. ,  RACHMADY, Willy ,  THOMAS, Nicole K. ,  RADOSAVLJEVIC, Marko ,  KAVALIEROS, Jack T.

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

公开(公告)号：EP4191655A2

公开(公告)日：2023-06-07

申请号：EP22204391.1

申请日：2022-10-28

申请人： INTEL Corporation

发明人： HUANG, Cheng-Ying ,  MORROW, Patrick ,  VENKATARAMAN, Arunshankar ,  MA, Sean T. ,  RACHMADY, Willy ,  THOMAS, Nicole K. ,  RADOSAVLJEVIC, Marko ,  KAVALIEROS, Jack T.

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.