公开(公告)号：EP4191655A3

公开(公告)日：2023-08-23

申请号：EP22204391.1

申请日：2022-10-28

申请人： INTEL Corporation

发明人： HUANG, Cheng-Ying ,  MORROW, Patrick ,  VENKATARAMAN, Arunshankar ,  MA, Sean T. ,  RACHMADY, Willy ,  THOMAS, Nicole K. ,  RADOSAVLJEVIC, Marko ,  KAVALIEROS, Jack T.

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

公开(公告)号：EP4060749A3

公开(公告)日：2023-05-24

申请号：EP22171115.3

申请日：2013-09-27

申请人： INTEL Corporation

发明人： DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  METZ, Matthew V.

IPC分类号： H01L29/778 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786 ,  H01L21/336 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00

摘要： Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：EP4141921A3

公开(公告)日：2023-05-17

申请号：EP22186480.4

申请日：2022-07-22

申请人： INTEL Corporation

发明人： RADOSAVLJEVIC, Marko ,  JUN, Kimin ,  THEN, Han Wui ,  FISCHER, Paul ,  THOMAS, Nicole ,  NORDEEN, Paul ,  HOFF, Thomas ,  KOIRALA, Pratik ,  TALUKDAR, Tushar

IPC分类号： H01L21/8258 ,  H01L21/02 ,  H01L27/085 ,  H01L27/06

摘要： Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer (106B) including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins (104) including silicon. A device layer (108) is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：EP4138124A2

公开(公告)日：2023-02-22

申请号：EP22184070.5

申请日：2022-07-11

申请人： INTEL Corporation

发明人： THEN, Han Wui ,  RADOSAVLJEVIC, Marko

IPC分类号： H01L23/522 ,  H01L29/76

摘要： High voltage metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：EP4060749A2

公开(公告)日：2022-09-21

申请号：EP22171115.3

申请日：2013-09-27

申请人： INTEL Corporation

发明人： DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  METZ, Matthew V.

IPC分类号： H01L29/778 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786 ,  H01L21/336 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00

摘要： Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：EP3748684A3

公开(公告)日：2021-03-10

申请号：EP20188064.8

申请日：2013-09-27

申请人： INTEL Corporation

发明人： DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  METZ, Matthew V.

IPC分类号： H01L29/778 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786 ,  H01L21/336 ,  H01L29/423

摘要： Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：EP3050091B1

公开(公告)日：2019-04-10

申请号：EP13894881.5

申请日：2013-09-27

申请人： Intel Corporation

发明人： PILLARISETTY, Ravi ,  DASGUPTA, Sansaptak ,  GOEL, Niti ,  LE, Van H. ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  RACHMADY, Willy ,  KAVALIEROS, Jack T. ,  CHU-KUNG, Benjamin ,  KENNEL, Harold W. ,  CEA, Stephen M. ,  CHAU, Robert S.

IPC分类号： H01L21/8234 ,  H01L29/267 ,  H01L29/165 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16

公开(公告)号：EP3314659A1

公开(公告)日：2018-05-02

申请号：EP15896569.9

申请日：2015-06-26

申请人： INTEL Corporation

发明人： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  CHAU, Robert S.

IPC分类号： H01L29/778 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7786 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462

摘要： Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：EP3238243A1

公开(公告)日：2017-11-01

申请号：EP14909269.4

申请日：2014-12-26

申请人： Intel Corporation

发明人： DEWEY, Gilbert ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy ,  GHANI, Tahir ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S. ,  GARDNER, Sanaz K. ,  RADOSAVLJEVIC, Marko ,  GLASS, Glenn A.

IPC分类号： H01L21/762 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

摘要翻译： 集成电路管芯包括用于通过从沟道材料下方移除一部分子鳍状物材料而形成的晶体管的沟道材料的四栅器件纳米线（例如，单一材料或成为MOS器件的沟道的堆叠） 其中子翅片材料在纵横比捕获（ART）沟槽中生长。 在某些情况下，在形成这种纳米线时，可能会去除通道下的有缺陷的鳍片材料或区域。 这种去除隔离鳍片沟道，去除鳍片缺陷和泄漏路径，并且形成具有四个暴露表面的沟道材料的纳米线，栅极材料可以在其上形成。

公开(公告)号：EP3120385A1

公开(公告)日：2017-01-25

申请号：EP14886535.5

申请日：2014-03-18

申请人： Intel Corporation

发明人： MUKHERJEE, Niloy ,  DOYLE, Brian S. ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  THEN, Han Wui ,  RAO, Valluri R. ,  CHAU, Robert S.

IPC分类号： H01L29/04 ,  H01L21/763

CPC分类号： H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

摘要： Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

摘要翻译： 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料以及设置在柔性衬底和多晶半导体材料之间和之间的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。