公开(公告)号：EP4109525A2

公开(公告)日：2022-12-28

申请号：EP22160232.9

申请日：2022-03-04

申请人： INTEL Corporation

发明人： DASU, Aravind ,  WEBER, Scott ,  GUTALA, Ravi ,  IYER, Mahesh ,  NURVITADHI, Eriko ,  SRINIVASAN, Archanna ,  ATSATT, Sean ,  BALL, James

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17768

摘要： A three dimensional circuit system (100) includes first (101) and second (102) integrated circuit (IC) dies. The first IC die (101) includes programmable logic circuits (16 times 210) arranged in sectors and first programmable interconnection circuits (221, 222) having first router circuits (231, 232). The second IC die (102) includes non-programmable circuits (270-285) arranged in regions and second programmable interconnection circuits (223, 224) having second router circuits (233, 234). Each of the regions in the second IC die (102) is vertically aligned with at least one of the sectors in the first IC die (101). Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection (255, 258). The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits (16 times 210) and the non-programmable circuits (270-285) through the first and second router circuits (231, 232, 233, 234). The circuit system (100) may include additional IC dies (fig. 3: 303, 304). The first and second IC dies (101, 102) and any additional IC dies are coupled in a vertically stacked configuration.

公开(公告)号：EP3324298A1

公开(公告)日：2018-05-23

申请号：EP17199050.0

申请日：2017-10-27

申请人： INTEL Corporation

发明人： DASU, Aravind ,  WEBER, Scott ,  TAN, Jun Pin ,  RAHMAN, Arifur

IPC分类号： G06F15/78

CPC分类号： G06F3/0629 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0673 ,  G06F15/7871 ,  G11C5/02 ,  G11C5/06 ,  Y02D10/12 ,  Y02D10/13

摘要： A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

公开(公告)号：EP4109525A3

公开(公告)日：2023-01-11

申请号：EP22160232.9

申请日：2022-03-04

申请人： INTEL Corporation

发明人： DASU, Aravind ,  WEBER, Scott ,  GUTALA, Ravi ,  IYER, Mahesh ,  NURVITADHI, Eriko ,  SRINIVASAN, Archanna ,  ATSATT, Sean ,  BALL, James

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17768

摘要： A three dimensional circuit system (100) includes first (101) and second (102) integrated circuit (IC) dies. The first IC die (101) includes programmable logic circuits (16 times 210) arranged in sectors and first programmable interconnection circuits (221, 222) having first router circuits (231, 232). The second IC die (102) includes non-programmable circuits (270-285) arranged in regions and second programmable interconnection circuits (223, 224) having second router circuits (233, 234). Each of the regions in the second IC die (102) is vertically aligned with at least one of the sectors in the first IC die (101). Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection (255, 258). The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits (16 times 210) and the non-programmable circuits (270-285) through the first and second router circuits (231, 232, 233, 234). The circuit system (100) may include additional IC dies (fig. 3: 303, 304). The first and second IC dies (101, 102) and any additional IC dies are coupled in a vertically stacked configuration.

公开(公告)号：EP4300349A1

公开(公告)日：2024-01-03

申请号：EP23166312.1

申请日：2023-04-03

申请人： INTEL Corporation

发明人： PENG, Yi ,  WEBER, Scott ,  IYER, Mahesh

IPC分类号： G06F30/343 ,  G06F30/327 ,  G06F111/02

摘要： A compilation design method (120) that uses cloud computing resources and/or distributed computing resources to compile initial user designs (122). The initial user design (122)n for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic (124). The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF (144) is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs (142).

公开(公告)号：EP4106201A1

公开(公告)日：2022-12-21

申请号：EP22159985.5

申请日：2022-03-03

申请人： INTEL Corporation

发明人： SRINIVASAN, Archanna ,  GUTALA, Ravi ,  WEBER, Scott ,  DASU, Aravind ,  IYER, Mahesh ,  NURVITADHI, Eriko

IPC分类号： H03K19/00 ,  H03K19/17772 ,  H03K19/17784 ,  H03K19/17728

摘要： A circuit system includes a first integrated circuit die (312) having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die (313) having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors (721-723) in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

公开(公告)号：EP3330866A1

公开(公告)日：2018-06-06

申请号：EP17197872.9

申请日：2017-10-23

申请人： INTEL Corporation

发明人： DASU, Aravind ,  WEBER, Scott ,  TAN, Jun Pin ,  RAHMAN, Arifur

IPC分类号： G06F15/78 ,  G06F9/46

CPC分类号： G06F9/5027 ,  G06F9/46 ,  G06F9/4843 ,  G06F15/7867 ,  G11C5/02 ,  Y02D10/12 ,  Y02D10/13

摘要： A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.

公开(公告)号：EP4105931A1

公开(公告)日：2022-12-21

申请号：EP22160217.0

申请日：2022-03-04

申请人： INTEL Corporation

发明人： WEBER, Scott ,  KHAN, Jawad ,  GANUSOV, Ilya ,  LANGHAMMER, Martin ,  ADILETTA, Matthew ,  MAGEE, Terence ,  COULSON, Richard ,  FAZIO, Albert ,  GUTALA, Ravi ,  DASU, Aravind ,  IYER, Mahesh

IPC分类号： G11C5/02 ,  G11C11/00 ,  H01L27/11578 ,  G11C5/06

摘要： A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：EP4105763A1

公开(公告)日：2022-12-21

申请号：EP22160259.2

申请日：2022-03-04

申请人： INTEL Corporation

发明人： SRINIVASAN, Archanna ,  GUTALA, Ravi ,  WEBER, Scott ,  DASU, Aravind ,  IYER, Mahesh ,  NURVITADHI, Eriko

IPC分类号： G06F1/26 ,  G06F1/32 ,  G05F1/575 ,  G05F1/577

摘要： A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

公开(公告)号：EP4105762A1

公开(公告)日：2022-12-21

申请号：EP22160224.6

申请日：2022-03-04

申请人： INTEL Corporation

发明人： GUTALA, Ravi ,  NURVITADHI, Eriko ,  SRINIVASAN, Archanna ,  DASU, Aravind ,  WEBER, Scott ,  IYER, Mahesh

IPC分类号： G06F1/26 ,  G06F1/32

摘要： A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.