公开(公告)号：EP4300349A1

公开(公告)日：2024-01-03

申请号：EP23166312.1

申请日：2023-04-03

申请人： INTEL Corporation

发明人： PENG, Yi ,  WEBER, Scott ,  IYER, Mahesh

IPC分类号： G06F30/343 ,  G06F30/327 ,  G06F111/02

摘要： A compilation design method (120) that uses cloud computing resources and/or distributed computing resources to compile initial user designs (122). The initial user design (122)n for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic (124). The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF (144) is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs (142).

公开(公告)号：EP4383119A1

公开(公告)日：2024-06-12

申请号：EP23199077.1

申请日：2023-09-22

申请人： INTEL Corporation

发明人： NAGAR, Krishna ,  KRUEGER, Nathan ,  PENG, Yi ,  GORDON, Brandon ,  VENKITASUBRAMANI, Anand

IPC分类号： G06F30/327

CPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F2115/1020200101 ,  G06F2117/0820200101

摘要： Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

公开(公告)号：EP4180963A1

公开(公告)日：2023-05-17

申请号：EP22200254.5

申请日：2022-10-07

申请人： Intel Corporation

发明人： NAGAR, Krishna ,  GORDON, Brandon ,  PENG, Yi

IPC分类号： G06F11/10

摘要： An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.