公开(公告)号：EP0657805A1

公开(公告)日：1995-06-14

申请号：EP94309074.6

申请日：1994-12-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MOTOROLA INC.

发明人： Burgess, Bradley G. ,  Elliott, Timothy A. ,  Olson, Christopher H. ,  Potter, Terence M.

IPC分类号： G06F7/50 ,  G06F5/01

CPC分类号： G06F7/485 ,  G06F5/012

摘要： A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

公开(公告)号：EP0368144A3

公开(公告)日：1990-11-14

申请号：EP89120284.8

申请日：1989-11-02

申请人： MOTOROLA, INC.

发明人： Fourcroy, Antone Louis ,  McDermott, Mark William ,  Dunn, John P. ,  Burgess, Bradley G.

IPC分类号： G06F1/32

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/30167

摘要： An integrated circuit microcomputer (10) enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system (16) within the microcomputer. This subsystem (16) then shuts down the clock signals to the remainder of the microcomputer (10), leaving only this sub-system (16) active. The active sub-system (16) performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode.

公开(公告)号：EP0368144B1

公开(公告)日：1996-02-07

申请号：EP89120284.8

申请日：1989-11-02

申请人： MOTOROLA, INC.

发明人： Fourcroy, Antone Louis ,  McDermott, Mark William ,  Dunn, John P. ,  Burgess, Bradley G.

IPC分类号： G06F1/32

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/30167

公开(公告)号：EP0368144A2

公开(公告)日：1990-05-16

申请号：EP89120284.8

申请日：1989-11-02

申请人： MOTOROLA, INC.

发明人： Fourcroy, Antone Louis ,  McDermott, Mark William ,  Dunn, John P. ,  Burgess, Bradley G.

IPC分类号： G06F1/32

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/30167

摘要： An integrated circuit microcomputer (10) enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system (16) within the microcomputer. This subsystem (16) then shuts down the clock signals to the remainder of the microcomputer (10), leaving only this sub-system (16) active. The active sub-system (16) performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode.

摘要翻译： 集成电路微计算机（10）响应于执行LPSTOP指令而进入低功率模式。 只有重置事件和具有足够高优先级的中断事件才能通过中断掩码，才能使低功耗模式终止。 LPSTOP指令将立即数据加载到状态寄存器中，复位中断屏蔽位。 然后，通过专用总线周期将中断屏蔽写入微机内的子系统（16）中的中断屏蔽寄存器。 该子系统（16）然后将时钟信号关闭到微计算机（10）的其余部分，仅留下该子系统（16）有效。 有源子系统（16）在低功率模式期间对接收到的中断请求的优先级进行中断屏蔽的比较。