公开(公告)号：EP0872885A2

公开(公告)日：1998-10-21

申请号：EP98301844.1

申请日：1998-03-12

申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Fiegl, Bernhard ,  Glashauser, Walter ,  Levy, Max G. ,  Nastasi, Victor R,

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053

摘要： A method of isolation in silicon integrated circuit processing overfills the trench by a fill margin, deposits a temporary layer of poly (120) having a thickness less than the trench depth by the thickness of an oxide polish stop (130), so that the top of the polish stop is coplanar with the top of the fill layer outside the trench; the temporary layer is polished outside the trench, using the fill layer and the polish stop layer (130) as polish stops; the polish stop layer is removed together with the same thickness of the fill layer and temporary layer, preserving planarity that is destroyed by selectively etching the fill layer; the remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.

摘要翻译： 将衬底中的平面化平坦化到参考表面的方法包括沉积比沟槽更厚的填充层（110）并且在参考表面上方并且沉积具有沟槽深度的厚度减去一个的临时填充层（120） 抛光边缘高于参考面。 沉积具有抛光边缘厚度的抛光阻挡层（130）和形成的抛光掩模（40）。 停止层被去除在掩模之外，并且临时层被抛光以使上表面与第一填充层的顶表面共面。 蚀刻停止层和临时层，去除抛光停止层并在沟槽上方留下填充层的盖，并保留中间平面。 然后通过蚀刻覆盖层外部的填充层而使其破坏，使得第二填充顶表面与沟槽中的第一填充层共面。 然后蚀刻临时填充层，留下第一填充层，然后抛光，停止在参考表面上。

公开(公告)号：EP0875927A3

公开(公告)日：1999-07-07

申请号：EP98303125.3

申请日：1998-04-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Levy, Max Gerald ,  Fiegl, Bernhard ,  Glashauser, Walter ,  Prein, Frank

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/76229

摘要： FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

公开(公告)号：EP0875927B1

公开(公告)日：2004-06-16

申请号：EP98303125.3

申请日：1998-04-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Levy, Max Gerald ,  Fiegl, Bernhard ,  Glashauser, Walter ,  Prein, Frank

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/76229

公开(公告)号：EP0872885A3

公开(公告)日：1999-06-09

申请号：EP98301844.1

申请日：1998-03-12

申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Fiegl, Bernhard ,  Glashauser, Walter ,  Levy, Max G. ,  Nastasi, Victor R,

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053

摘要： A method of isolation in silicon integrated circuit processing overfills the trench by a fill margin, deposits a temporary layer of poly (120) having a thickness less than the trench depth by the thickness of an oxide polish stop (130), so that the top of the polish stop is coplanar with the top of the fill layer outside the trench; the temporary layer is polished outside the trench, using the fill layer and the polish stop layer (130) as polish stops; the polish stop layer is removed together with the same thickness of the fill layer and temporary layer, preserving planarity that is destroyed by selectively etching the fill layer; the remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.

公开(公告)号：EP0910117A2

公开(公告)日：1999-04-21

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105

CPC分类号： H01L21/31053

摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

摘要翻译： 一种用于防止对下方设置一个台面的衬垫氮化物层上的基材的CMP引起的（化学机械抛光）损伤的方法。 垫氮化物层被设置在共形地沉积介电层的下方。 所述介电层设置下方的共形沉积多晶硅层。 该方法包括：平坦化所述多晶硅层至至少使用CMP以暴露电介质层的第一区域中的电介质层的表面上。 该方法包括：通过使用第一蚀刻参数的电介质层的第一区域进行蚀刻进一步部分。 第一蚀刻参数包括蚀刻源气体的缺陷确实基本上选择性的衬垫氮化物层，以防止垫氮化物层从即使在CMP的情况下，通过被蚀刻。 此外，还有被包含因此部分地穿过介电层的第一区域中去除蚀刻后的多晶硅层。

公开(公告)号：EP0910117B1

公开(公告)日：2002-09-04

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/31053

公开(公告)号：EP0872885B1

公开(公告)日：2001-11-28

申请号：EP98301844.1

申请日：1998-03-12

申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Fiegl, Bernhard ,  Glashauser, Walter ,  Levy, Max G. ,  Nastasi, Victor R,

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053

公开(公告)号：EP0910117A3

公开(公告)日：1999-06-02

申请号：EP98305084.0

申请日：1998-06-26

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Levy, Max G. ,  Fiegl, Bernhard ,  Bergner, Wolfgang ,  Goth, George R. ,  Parries, Paul ,  Sendelbach, Matthew J. ,  Wang, Ting-Hao ,  Wille, William C. ,  Wittmann, Juergen

IPC分类号： H01L21/3105

CPC分类号： H01L21/31053

摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

摘要翻译： 一种用于防止CMP引起的（化学机械抛光）损坏设置在台面的垫氮化物层下方的衬底的方法。 垫氮化物层设置在共形沉积的电介质层下方。 介电层设置在共形沉积的多晶硅层下方。 该方法包括使用CMP将多晶硅层平坦化到至少介电层的表面以暴露介电层的第一区域。 该方法还包括使用第一蚀刻参数部分地蚀刻介电层的第一区域。 第一蚀刻参数包括对衬垫氮化物层基本上具有选择性的蚀刻剂源气体，以防止衬垫氮化物层即使在存在CMP缺陷的情况下也被蚀刻穿过。 此外，还包括在蚀刻之后部分地通过介电层的第一区域去除多晶硅层。

公开(公告)号：EP0875927A2

公开(公告)日：1998-11-04

申请号：EP98303125.3

申请日：1998-04-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Levy, Max Gerald ,  Fiegl, Bernhard ,  Glashauser, Walter ,  Prein, Frank

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/76229

摘要： FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

摘要翻译： FET器件（10）使用涂覆有衬垫（14）的半导体衬底（11）上的STI制造，在衬底（14）上形成凸起的有源硅器件区域和在掺杂硅衬底上由衬垫结构封装的虚拟有源硅台面（12） 垫结构。 在平台（12）上方具有保形突起，在器件（10）上沉积保形覆盖层氧化硅（22）层。 然后在覆层氧化硅层（22）上的多晶硅膜（24）上沉积有台面（12）之上的保形突起。 在CMP抛光步骤中去除多晶硅膜突起，其继续直到氧化硅层（22）暴露在焊盘结构（14）上。 接下来，在平台氧化硅层（12）上的保形二氧化硅层（22）的选择性RIE局部蚀刻，接着通过共形覆盖氧化硅层（22）的CMP平坦化，其将氧化硅层转换成平面氧化硅层 ，使用焊盘氮化硅（14）作为蚀刻停止。