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公开(公告)号：EP3767454A1
公开(公告)日：2021-01-20
申请号：EP20186217.4
申请日：2020-07-16
发明人： ELLIOTT, Sam , KÄLLÉN, Jonas , VAN BENTHEM, Casper
摘要： Adder circuits and associated methods are disclosed, for processing a set of at least three floating-point numbers to be added together. The method comprises identifying (606), from among the at least three numbers, at least two numbers that have the same sign - that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together (608) using one or more same-sign floating-point adders (120, 220a, 320, 420). A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
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公开(公告)号：EP3588443A1
公开(公告)日：2020-01-01
申请号：EP19182750.0
申请日：2019-06-26
发明人： VAN BENTHEM, Casper
摘要： Conservative rasterization hardware is described that comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.
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公开(公告)号：EP3882764A1
公开(公告)日：2021-09-22
申请号：EP21163266.6
申请日：2021-03-17
发明人： VAN BENTHEM, Casper
IPC分类号： G06F9/38 , G06F13/364 , G06F9/52
摘要： Methods of arbitrating between requestors and a shared resource are described. The method comprises generating a vector with one bit per requestor, each initially set to one. Based on a plurality of select signals (one per decision node in a first layer of a binary decision tree, where each select signal is configured to be used by the corresponding decision node to select one of two child nodes), bits in the vector corresponding to non-selected requestors are set to zero. The method is repeated for each subsequent layer in the binary decision tree, based on the select signals for the decision nodes in those layers. The resulting vector is a one-hot vector (in which only a single bit has a value of one). Access to the shared resource is granted, for a current processing cycle, to the requestor corresponding to the bit having a value of one.
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公开(公告)号：EP3872621A1
公开(公告)日：2021-09-01
申请号：EP21158917.1
申请日：2021-02-24
发明人： VAN BENTHEM, Casper
IPC分类号： G06F7/499
摘要： Apparatus comprising hardware logic arranged to normalise an n-bit input number is described. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
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公开(公告)号：EP3588442A1
公开(公告)日：2020-01-01
申请号：EP19182636.1
申请日：2019-06-26
发明人： VAN BENTHEM, Casper
摘要： Conservative rasterization hardware is described that comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.
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公开(公告)号：EP3882780A1
公开(公告)日：2021-09-22
申请号：EP21163270.8
申请日：2021-03-17
发明人： VAN BENTHEM, Casper
IPC分类号： G06F13/364 , G06F9/52 , G06F9/38
摘要： Methods of arbitrating between requestors and a shared resource are described. For each processing cycle a plurality of select signals are generated and then used by decision nodes in a binary decision tree to select a requestor. The select signals are generated using valid bits and priority bits. Each valid bit corresponds to one of the requestors and indicates whether, in the processing cycle, the requestor is requesting access to the shared resource. Each priority bit corresponds one of the requestors and indicates whether, in the processing cycle, the requestor has priority. Corresponding valid bit and priority bits are combined in an AND logic element to generate a valid_and_priority bit for each requestor. Pair-wise OR-reduction is then performed on both the valid bits and the valid_and_priority bits to generate additional valid bits and valid_and_priority bits for sets of requestors and these are then used to generate the select signal.
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公开(公告)号：EP3608878A1
公开(公告)日：2020-02-12
申请号：EP19167185.8
申请日：2019-04-03
发明人： VAN BENTHEM, Casper
摘要： A graphics processing pipeline comprises hardware arrangements arranged to perform an edge test or a depth calculation. Each hardware arrangement comprises a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
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公开(公告)号：EP3159788B1
公开(公告)日：2018-08-29
申请号：EP16194577.9
申请日：2016-10-19
发明人： VAN BENTHEM, Casper , ELLIOTT, Sam
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/49963 , G06F7/552 , G06F7/5525 , G06F2207/5521
摘要： Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term. To be accompanied, when published, by FIG. 3 of the accompanying drawings.
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公开(公告)号：EP3159788A1
公开(公告)日：2017-04-26
申请号：EP16194577.9
申请日：2016-10-19
发明人： VAN BENTHEM, Casper , ELLIOTT, Sam
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/49963 , G06F7/552 , G06F7/5525 , G06F2207/5521
摘要： Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.
To be accompanied, when published, by FIG. 3 of the accompanying drawings.摘要翻译： 用于确定在输入浮点数上执行的倒数平方根操作的无限精确结果是否大于第一浮点精度中的特定数量的方法和系统。 该方法包括以第二较低浮点精度计算特定数量的平方; 计算由于第二浮点精度而导致的计算平方的误差; 通过计算乘以输入浮点数减去一的平方来计算第一浮点精度的第一增量值; 通过计算误差乘以输入浮点数加上第一增量值来计算第二增量值; 并基于第二增量项输出对倒数平方根运算的无限精确结果是否大于特定数的指示。 伴随着，当出版时，由图。 附图3。
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