利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

63 条记录 (耗时 0.015 秒)

    Method and apparatus for reducing rounding error when evaluating binary floating point polynomials
    4.
    发明公开
    Method and apparatus for reducing rounding error when evaluating binary floating point polynomials 失效
    用于舍入误差的降低方法和装置评价二进制Fliesskommapolynomialen时

    公开(公告)号：EP0738960A2

    公开(公告)日：1996-10-23

    申请号：EP96106006.8

    申请日：1996-04-17

    申请人： MOTOROLA, INC.

    发明人： Smith, Roger A.

    IPC分类号： G06F7/552

    CPC分类号： G06F7/552 ,  G06F7/483 ,  G06F7/49947 ,  G06F2207/5523

    摘要： Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zero th level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.

    摘要翻译： 可以当由第一评价二进制浮点多项式利用浮点单元（58）计算的第二和更高阶多项式项乘积之和被减小舍入误差。 接着，浮点单元（58）增加了一个零水平术语一阶系数的乘积和上独立变量，以形成一个“大”的术语。 浮点单元（58）计算为“小”一词的舍入误差，从“大”一词的计算得到的。 然后，将“小”术语被添加到的高阶项乘积之和，以形成一个“中间”一词。 最后，浮点单元（58）增加了“大”术语“中间”一词，以形成由低次项的计算中引入的舍入误差校正多项式结果。

    Method and circuit for calculating the reciprocal of the amplitude of a vector
    5.
    发明公开
    Method and circuit for calculating the reciprocal of the amplitude of a vector 失效
    Verfahren und Schaltungsanordnung zur Berechnung des Kehrwerts der Amplitude eines Vektors。

    公开(公告)号：EP0603794A1

    公开(公告)日：1994-06-29

    申请号：EP93120528.0

    申请日：1993-12-20

    申请人： FUJITSU LIMITED

    发明人： Kaku, Takashi, Fujitsu Ltd., 1015 Kami-kodanaka ,  Miyazawa, Hideo, Fujitsu Ltd., 1015 Kami-kodanaka

    IPC分类号： G06F7/552 ,  G06F15/347

    CPC分类号： G06F7/5525 ,  G06F7/4806 ,  G06F7/552 ,  G06F17/10 ,  G06F2207/5521 ,  G06F2207/5525

    摘要： The method and circuit find the reciprocal value of an input vector signal. The level of the input vector signal (X + jY) is first reduced to (X + jY)/ 2 in an overflow-preventing circuit. A power calculating circuit squares and adds the components of the level-reduced input vector signal, thereby obtaining a power value (X² + Y²)/2 . An initial value of a tap value (K), which represents the reciprocal value to be found, is multiplied twice by a multiplying circuit, thereby obtaining K²(X + Y)²/2 . Further, a differential circuit obtains an error signal (ΔK) = 1/2 - K²(X² + Y²)/2 by subtraction from a reference value. An updating circuit updates the tap value (K) by adding to it the error signal (ΔK). A loop consisting of the multiplication of the tap value, differential operation, and updating of the tap value, is repeated until the error signal (ΔK) is reduced to less than or equal to a predetermined value. The tap value (K) thus obtained is the desired reciprocal value 1/√(X² + Y²) of the amplitude of the input vector signal. The method and circuit can be used for amplitude normalization in a modem, for example.

    摘要翻译： 方法和电路找到输入向量信号的倒数值。 在溢出防止电路中，输入矢量信号（X + jY）的电平首先降低到（X + jY）/ 2。 功率计算电路对电平降低输入矢量信号的分量进行平方并相加，从而获得功率值（X 2 + Y 2）/ 2。 通过乘法电路将代表要发现的倒数值的抽头值（K）的初始值相乘2次，从而获得K 2（X + Y）2/2。 此外，差分电路通过从参考值减法来获得误差信号（DELTA K）= 1/2-K 2（X 2 + Y 2）/ 2。 更新电路通过向其加上误差信号（DELTA K）来更新抽头值（K）。 重复由抽头值，微分运算和抽头值的更新组成的回路，直到误差信号（DELTA K）减小到小于或等于预定值。 由此获得的抽头值（K）是输入矢量信号幅度的期望的互逆值1 / 2ROOT（X 2 + Y 2）。 例如，该方法和电路可用于调制解调器中的幅度归一化。

    Apparatus and method for approximating the magnitude of a complex number
    7.
    发明公开
    Apparatus and method for approximating the magnitude of a complex number 失效
    装置和用于近似复数的大小的方法。

    公开(公告)号：EP0264256A2

    公开(公告)日：1988-04-20

    申请号：EP87309031.0

    申请日：1987-10-13

    申请人： RAYTHEON COMPANY

    发明人： Jagodnik, Anthony J., Jr. ,  Evett, Ronald C.

    IPC分类号： G06F15/347

    CPC分类号： G06F7/4806 ,  G06F7/552 ,  G06F2207/5525

    摘要： This vector magnitude approximating method uses logarithms of vector's orthogonal components to select multiplier scaling constants (K x ,K y ) and to minimize arithmetic-function and hardware complexity. The vector magnitude is approximated by multiplying (20,22) each component (X,Y) of a complex number representing the vector by selected scaling constants (K x ,K y ) and then by summing (24) the two resulting products (K x X,K y Y). The scaling constants (K x ,K y ) are selected by feeding each orthogonal component (X,Y) into one of two identical logic arrays (10,12) which determine the base-2 logarithm of the absolute value of each component. The resulting logarithm values are fed, in parallel, into a third logic array (14) which outputs an address to real and imaginary constant read-only memory generators (16,18) for providing respective scaling constant pairs (K x ,K y ) which are used in computing the approximate magnitude of the vector or complex number. The apparatus is particularly applicable to a high-throughput, pipelined, digital signal processing application such as radar.

    摘要翻译： 该载体大小近似方法使用矢量的分量正交，选择乘法器缩放常量（KX，KY），并尽量减少算术功能和硬件复杂度的对数。 矢量大小由乘法的逼近（20,22）表示通过按比例缩放选择常数（KX，KY）和矢量复数的每个分量（X，Y），然后通过求和（24）在两个所得产品（KXX，KYY ）。 缩放常量（KX，KY）是通过将各正交分量（X，Y）中选出成两个相同的逻辑阵列中的一个（10,12）确定哪个矿每个分量的绝对值的基数为2的对数。 将所得的对数值被馈送，并联到第三逻辑阵列（14），其输出，以解决对实部和虚常数只读存储器发生器（16,18），用于提供respectivement比例常数对（KX，KY）哪些是 在计算向量或复数的近似大小使用。 该装置特别适用于高通量的，流水线，数字信号处理应用：如雷达。

    DIGITAL VALUE PROCESSOR
    8.
    发明授权
    DIGITAL VALUE PROCESSOR 有权
    数字处理器VALUE

    公开(公告)号：EP1137981B1

    公开(公告)日：2007-03-07

    申请号：EP99973136.7

    申请日：1999-11-03

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： SCHULIST, Matthias

    IPC分类号： G06F7/552

    CPC分类号： G06F7/552 ,  G06F2207/5523

    摘要： The present application relates to a device and method for processing a digital value to thereby determine an estimate of the square of said digital value. This is done by linearly approximating the square function with the help of anchor points that are powers of 2, such that the estimate of the square of a digital value xa is determined on the basis of a first processing value 2i, where 2i ≤x¿a? ∫2?i+1¿, and a second processing value (3x¿a? - 2?i+1¿). The present invention is advantageous in that it allows simple processing steps and a simple processing hardware. It is preferably applied to the mean signal power estimation of a digital signal being sent to a transmitter.

    DIGITAL VALUE PROCESSOR
    10.
    发明公开
    DIGITAL VALUE PROCESSOR 有权
    数字处理器VALUE

    公开(公告)号：EP1137981A1

    公开(公告)日：2001-10-04

    申请号：EP99973136.7

    申请日：1999-11-03

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON

    发明人： SCHULIST, Matthias

    IPC分类号： G06F7/552

    CPC分类号： G06F7/552 ,  G06F2207/5523

    摘要： The present application relates to a device and method for processing a digital value to thereby determine an estimate of the square of said digital value. This is done by linearly approximating the square function with the help of anchor points that are powers of 2, such that the estimate of the square of a digital value xa is determined on the basis of a first processing value 2i, where 2i ≤x¿a? ∫2?i+1¿, and a second processing value (3x¿a? - 2?i+1¿). The present invention is advantageous in that it allows simple processing steps and a simple processing hardware. It is preferably applied to the mean signal power estimation of a digital signal being sent to a transmitter.