公开(公告)号：EP3410603A1

公开(公告)日：2018-12-05

申请号：EP18173095.3

申请日：2018-05-18

Applicant: Infineon Technologies Austria AG

Inventor： BUFFA, Cesare ,  CARDES GARCIA, Fernando ,  HERNANDEZ-CORPORALES, Luis ,  QUINTERO ALONSO, Andres ,  WIESBAUER, Andreas

IPC: H03M1/60 ,  H03M3/00

CPC classification number: H03M3/496 ,  H03M1/504 ,  H03M1/60 ,  H03M3/438

Abstract: In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.