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公开(公告)号：EP3174106A1
公开(公告)日：2017-05-31
申请号：EP17151661.0
申请日：2011-09-30
申请人： Intel Corporation
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L29/49
CPC分类号： H01L21/823828 , H01L21/76897 , H01L21/823857 , H01L29/41791 , H01L29/495 , H01L29/51 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： An integrated circuit (IC) structure, comprising a fin having a source and a drain, wherein the fin comprises silicon, a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises a gate dielectric on the fin, wherein the gate dielectric comprises hafnium, silicon, and oxygen, an NMOS gate electrode on the gate dielectric, wherein the NMOS gate electrode comprises a first layer on the gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon, a second layer on the first layer, wherein the second layer comprises titanium, and a third layer on the second layer, wherein the third layer comprises tungsten, sidewalls on opposing sides of the NMOS gate electrode, a capping structure over the NMOS gate electrode, wherein the capping structure comprises silicon and nitrogen, a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and a contact extending through the dielectric layer to one of the source and the drain.
摘要翻译： 一种集成电路（IC）结构，包括具有源极和漏极的鳍片，其中所述鳍片包括硅，在所述源极和所述漏极之间的所述鳍片上的晶体管栅极，其中所述晶体管栅极包括所述鳍片上的栅极电介质，其中 所述栅极电介质包括铪，硅和氧，在所述栅极电介质上的NMOS栅极电极，其中所述NMOS栅极电极包括在所述栅极电介质上的第一层，其中所述第一层包括铝，钛和碳， 其中所述第二层包括钛的第一层以及所述第二层上的第三层，其中所述第三层包括钨，所述NMOS栅极电极的相对侧上的侧壁，所述NMOS栅极电极上的覆盖结构，其中所述覆盖结构 包括硅和氮，与所述侧壁相邻的介电层，其中所述介电层包括硅和氧，以及延伸穿过所述介电层的触点， 来源和排水渠之一。
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公开(公告)号：EP2761662A1
公开(公告)日：2014-08-06
申请号：EP11873428.4
申请日：2011-09-30
申请人： Intel Corporation
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823828 , H01L21/76897 , H01L21/823857 , H01L29/41791 , H01L29/495 , H01L29/51 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.
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公开(公告)号：EP3506367A1
公开(公告)日：2019-07-03
申请号：EP19156246.1
申请日：2011-09-30
申请人： Intel Corporation
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L27/092
摘要： An integrated circuit (IC) structure, comprising a fin having a source and a drain, wherein the fin comprises silicon, a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises a gate dielectric on the fin, wherein the gate dielectric comprises hafnium, silicon, and oxygen, an NMOS gate electrode on the gate dielectric, wherein the NMOS gate electrode comprises a first layer on the gate dielectric, wherein the first layer comprises aluminum, titanium, and carbon, a second layer on the first layer, wherein the second layer comprises titanium, and a third layer on the second layer, wherein the third layer comprises tungsten, sidewalls on opposing sides of the NMOS gate electrode, a capping structure over the NMOS gate electrode, wherein the capping structure comprises silicon and nitrogen, a dielectric layer adjacent the sidewalls, wherein the dielectric layer comprises silicon and oxygen, and a contact extending through the dielectric layer to one of the source and the drain.
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