公开(公告)号：EP3321967A1

公开(公告)日：2018-05-16

申请号：EP17201382.3

申请日：2017-11-13

申请人： MediaTek Inc.

发明人： LIN, Hslen-Hsin ,  YANG, Ming-Tzong ,  WAN, Wen-Kai

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L23/367 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0211 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/7851

摘要： The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

摘要翻译： 本发明提供了一种半导体器件。 该半导体器件包括并联布置的鳍状结构上的栅极结构。 每个鳍片结构在栅极结构的相对侧上具有漏极部分和源极部分。 漏极接触结构位于鳍结构的漏极部分之上。 源极接触结构位于鳍结构的源极部分之上。 第一数量的漏极通孔结构电连接到漏极接触结构。 第二量的源极过孔结构电连接到源极接触结构。 第一数量与第二数量之和大于或等于2，第一数量与第二数量的总和小于或等于翅片结构数量的两倍。

公开(公告)号：EP3278365A1

公开(公告)日：2018-02-07

申请号：EP16705652.2

申请日：2016-02-03

申请人： Qualcomm Incorporated

发明人： SONG, Stanley Seungchul ,  XU, Jeffrey Junhao ,  RIM, Kern ,  YANG, Da ,  ZHU, John Jianhong ,  BAO, Junjing ,  MOJUMDER, Niladri Narayan ,  MACHKAOUTSAN, Vladimir ,  BADAROGLU, Mustafa ,  YEAP, Choh Fei

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

CPC分类号： H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

公开(公告)号：EP3084815A4

公开(公告)日：2018-01-03

申请号：EP13899890

申请日：2013-12-19

申请人： INTEL CORP

发明人： WEBB MILTON CLAIR ,  BOHR MARK ,  GHANI TAHIR ,  LIAO SZUYA S

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：EP3188227A1

公开(公告)日：2017-07-05

申请号：EP16204646.0

申请日：2016-12-16

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/417

CPC分类号： H01L21/823871 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

摘要： A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type regions, forming a first epitaxial layer on each fin structure on both sides of the gate structure in the P-type regions, forming a P-type doped first covering layer on each first epitaxial layer, forming a second epitaxial layer on each fin structure on both sides of the gate structure in the N-type regions, forming an N-type doped second covering layer on each second epitaxial layer, and forming a titanium-containing silicification layer on the first covering layer and the second covering layer. The method further includes performing a first annealing process to let titanium ions in the silicification layer diffuse into the first covering layer to form a first metal silicide layer and into the second covering layer to form a second metal silicide layer.

摘要翻译： 一种用于制造鳍式场效应晶体管器件的方法，包括：形成鳍状结构，其中每个在P型区域和N型区域的顶部具有栅极结构;在栅极结构两侧的每个鳍状结构上形成第一外延层 在P型区域中，在每个第一外延层上形成P型掺杂的第一覆盖层，在N型区域中的栅极结构两侧的每个鳍状结构上形成第二外延层，形成N型 在每个第二外延层上形成掺杂有掺杂的第二覆盖层，以及在第一覆盖层和第二覆盖层上形成含钛硅化层。 该方法进一步包括执行第一退火工艺以使硅化层中的钛离子扩散到第一覆盖层中以形成第一金属硅化物层并且进入第二覆盖层中以形成第二金属硅化物层。

公开(公告)号：EP3182461A1

公开(公告)日：2017-06-21

申请号：EP15200415.6

申请日：2015-12-16

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： HELLINGS, Geert ,  BOSCHKE, Roman ,  LINTEN, Dimitri ,  HORIGUCHI, Naoto

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： The present invention relates to a semiconductor fin device (100) comprising at least three fins (102-106) arranged in parallel and protruding out from a substrate (111), the fins are separated from each other by shallow trench isolation structures (101), at least a first (102) and a second (106) of the fins protruding to a level higher than an upper surface (107) of the shallow trench isolation structures, the parallel fins are spaced with a first fin spacing (108), with at least one third fin arranged in between a first and a second fin, wherein in a non-protruding region (110) the third fin extends to a level below or equal to the upper surface of the shallow trench isolation structures.

摘要翻译： 本发明涉及一种包括至少三个平行排列并从衬底（111）突出的鳍（102-106）的半导体鳍式器件（100），所述鳍通过浅沟槽隔离结构（101）彼此分离， ，所述鳍片中的至少第一（102）和第二（106）突出到比所述浅沟槽隔离结构的上表面（107）高的水平，所述平行鳍片以第一鳍片间隔（108）隔开， 其中至少一个第三鳍片被布置在第一鳍片与第二鳍片之间，其中在非突出区域（110）中，第三鳍片延伸至低于或等于浅沟槽隔离结构的上表面的水平。

公开(公告)号：EP3144960A3

公开(公告)日：2017-06-21

申请号：EP16183571.5

申请日：2016-08-10

申请人： Renesas Electronics Corporation

发明人： Yamashita, Tomohiro

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/12 ,  H01L29/417 ,  H01L27/1157 ,  H01L27/11521

CPC分类号： H01L27/11521 ,  H01L21/28282 ,  H01L21/823431 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

摘要： A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

公开(公告)号：EP3084815A1

公开(公告)日：2016-10-26

申请号：EP13899890.1

申请日：2013-12-19

申请人： Intel Corporation

发明人： WEBB, Milton Clair ,  BOHR, Mark ,  GHANI, Tahir ,  LIAO, Szuya S.

IPC分类号： H01L21/336

CPC分类号： H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：EP2725620A3

公开(公告)日：2014-09-24

申请号：EP13185519.9

申请日：2013-09-23

申请人： Samsung Electronics Co., Ltd

发明人： Song, Tae Joong ,  Kim, Gyu Hong ,  Park, Jae Ho ,  Jung, Jong Hoon

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L29/41791 ,  H01L29/785

摘要： A fin Field Effect Transistor (finFET) arrangement according to the invention can includes a source region and a drain region of the finFET, as well as a gate of the finFET crossing over a fin of the finFET between the source and drain regions. First and second silicide layers are formed on the source and drain regions respectively. The first and second silicide layers include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces have different sizes.

公开(公告)号：EP2761662A1

公开(公告)日：2014-08-06

申请号：EP11873428.4

申请日：2011-09-30

申请人： Intel Corporation

发明人： PRADHAN, Sameer S. ,  BERGSTROM, Daniel, B. ,  CHUN, Jin-Sung ,  CHIU, Julia

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/76897 ,  H01L21/823857 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：EP2725620A2

公开(公告)日：2014-04-30

申请号：EP13185519.9

申请日：2013-09-23

申请人： Samsung Electronics Co., Ltd

发明人： Song, Tae Joong ,  Kim, Gyu Hong ,  Park, Jae Ho ,  Jung, Jong Hoon

IPC分类号： H01L29/417 ,  H01L29/78

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L29/41791 ,  H01L29/785

摘要： A fin Field Effect Transistor (finFET) arrangement according to the invention can includes a source region and a drain region of the finFET, as well as a gate of the finFET crossing over a fin of the finFET between the source and drain regions. First and second silicide layers are formed on the source and drain regions respectively. The first and second silicide layers include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces have different sizes.

摘要翻译： 根据本发明的鳍状场效应晶体管（finFET）装置可以包括finFET的源极区域和漏极区域以及在源极和漏极区域之间的finFET的鳍上交叉的finFET的栅极。 分别在源极和漏极区域上形成第一和第二硅化物层。 第一和第二硅化物层包括面对栅极交叉的栅极的相应的第一和第二表面，其中第一表面和第二表面具有不同的尺寸。