公开(公告)号：EP3588502A2

公开(公告)日：2020-01-01

申请号：EP19175812.7

申请日：2019-05-21

申请人： Intel Corporation

发明人： MANIPATRUNI, Sasikanth ,  GOSAVI, Tanay ,  YOUNG, Ian ,  NIKONOV, Dmitri

IPC分类号： G11C11/16 ,  H01L21/768 ,  H01L27/06 ,  H01L27/22

摘要： A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

公开(公告)号：EP3985740A3

公开(公告)日：2022-06-29

申请号：EP21192898.1

申请日：2021-08-24

申请人： INTEL Corporation

发明人： MAXEY, Kirby ,  PENUMATCHA, Ashish ,  NAYLOR, Carl ,  DOROW, Chelsey ,  O'BRIEN, Kevin ,  SHIVARAMAN, Shriram ,  GOSAVI, Tanay ,  AVCI, Uygar

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423

摘要： A transistor (100) includes two-dimensional materials. In some embodiments, the transistor may include a first two-dimensional channel material (102) and a second two-dimensional source/drain material (104) in a source/drain, and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material (102) in a channel and a second two-dimensional material (104) in a source/drain, wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

公开(公告)号：EP3996149A1

公开(公告)日：2022-05-11

申请号：EP21197263.3

申请日：2021-09-16

申请人： INTEL Corporation

发明人： AVCI, Uygar ,  OBRIEN, Kevin ,  SHIVARAMAN, Shriram ,  GOSAVI, Tanay ,  PENUMATCHA, Ashish Verma ,  NAYLOR, Carl ,  MAXEY, Kirby ,  DOROW, Chelsey ,  LEE, Sudarat

IPC分类号： H01L29/778 ,  H01L29/739 ,  H01L21/336 ,  H01L21/331 ,  H01L29/417 ,  H01L29/06 ,  H01L29/24

摘要： Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer (354) above a substrate (352). A first gate stack (362', 364') is on the insulator layer. A 2D channel material layer (356) is on the first gate stack. A second gate stack (364, 362) is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact (374) is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact (374) is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：EP4020557A3

公开(公告)日：2022-08-31

申请号：EP21210305.5

申请日：2021-11-24

申请人： INTEL Corporation

发明人： DOROW, Chelsey ,  O´BRIEN, Kevin ,  NAYLOR, Carl ,  AVCI, Uygar, E. ,  LEE, Sudarat ,  PENUMATCHA, Ashish Verma ,  LIN, Chia-Ching ,  GOSAVI, Tanay ,  SHIVARAMAN, Shriram ,  MAXEY, Kirby

IPC分类号： H01L27/092 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/51 ,  H01L29/775

摘要： A transistor includes a channel layer (102) including a transition metal dichalcogenide (TMD) material, an encapsulation layer (104) on a first portion of the channel layer, a gate electrode (108) above the encapsulation layer, a gate dielectric layer (106) between the gate electrode and the encapsulation layer. The transistor further includes a source contact (110) on a second portion of the channel layer and a drain contact (112) on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：EP3985740A2

公开(公告)日：2022-04-20

申请号：EP21192898.1

申请日：2021-08-24

申请人： INTEL Corporation

发明人： MAXEY, Kirby ,  PENUMATCHA, Ashish ,  NAYLOR, Carl ,  DOROW, Chelsey ,  O'BRIEN, Kevin ,  SHIVARAMAN, Shriram ,  GOSAVI, Tanay ,  AVCI, Uygar

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423

摘要： A transistor (100) includes two-dimensional materials. In some embodiments, the transistor may include a first two-dimensional channel material (102) and a second two-dimensional source/drain material (104) in a source/drain, and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material (102) in a channel and a second two-dimensional material (104) in a source/drain, wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

公开(公告)号：EP4020557A2

公开(公告)日：2022-06-29

申请号：EP21210305.5

申请日：2021-11-24

申请人： INTEL Corporation

发明人： DOROW, Chelsey ,  O´BRIEN, Kevin ,  NAYLOR, Carl ,  AVCI, Uygar, E. ,  LEE, Sudarat ,  PENUMATCHA, Ashish Verma ,  LIN, Chia-Ching ,  GOSAVI, Tanay ,  SHIVARAMAN, Shriram ,  MAXEY, Kirby

IPC分类号： H01L27/092 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/51 ,  H01L29/775

摘要： A transistor includes a channel layer (102) including a transition metal dichalcogenide (TMD) material, an encapsulation layer (104) on a first portion of the channel layer, a gate electrode (108) above the encapsulation layer, a gate dielectric layer (106) between the gate electrode and the encapsulation layer. The transistor further includes a source contact (110) on a second portion of the channel layer and a drain contact (112) on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：EP3588502A3

公开(公告)日：2020-03-25

申请号：EP19175812.7

申请日：2019-05-21

申请人： Intel Corporation

发明人： MANIPATRUNI, Sasikanth ,  GOSAVI, Tanay ,  YOUNG, Ian ,  NIKONOV, Dmitri

IPC分类号： G11C11/16 ,  H01L21/768 ,  H01L27/06 ,  H01L27/22

摘要： A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

公开(公告)号：EP3591701A1

公开(公告)日：2020-01-08

申请号：EP19175815.0

申请日：2019-05-21

申请人： INTEL Corporation

发明人： SMITH, Angeline ,  YOUNG, Ian ,  OGUZ, Kaan ,  MANIPATRUNI, Sasikanth ,  WIEGAND, Christopher ,  O'BRIEN, Kevin ,  RAHMAN, Tofizur ,  SATO, Noriyuki ,  BUFORD, Benjamin ,  GOSAVI, Tanay

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： An insertion layer (103) for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode (102) and the free magnetic layer (112), memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

公开(公告)号：EP4156298A1

公开(公告)日：2023-03-29

申请号：EP22191307.2

申请日：2022-08-19

申请人： INTEL Corporation

发明人： AVCI, Uygar ,  SHIVARAMAN, Shriram ,  GOSAVI, Tanay ,  PENUMATCHA, Ashish Verma ,  NAYLOR, Carl ,  MAXEY, Kirby ,  DOROW, Chelsey ,  O'BRIEN, Kevin

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/423 ,  H01L29/24

摘要： Transistors, devices, systems, and methods are discussed related to transistors including a number of 2D material channel layers and source and drain control electrodes coupled to source and drain control regions of the 2D material channels. The source and drain control electrodes (106, 107) are on opposite sides of a gate electrode (104), which controls a channel region (129) of the 2D material channels (102). The source and drain control electrodes provide for reduced contact resistance of the transistor, the ability to create complex logic gates, and other advantages.

公开(公告)号：EP4152411A1

公开(公告)日：2023-03-22

申请号：EP22191095.3

申请日：2022-08-18

申请人： INTEL Corporation

发明人： MAXEY, Kirby ,  PENUMATCHA, Ashish Verma ,  O'BRIEN, Kevin P. ,  DOROW, Chelsey ,  AVCI, Uygar E. ,  LEE, Sudarat ,  NAYLOR, Carl ,  GOSAVI, Tanay

IPC分类号： H01L29/786 ,  H01L29/778

摘要： Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.