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15 条记录 (耗时 0.015 秒)

    MECHANISM TO CONTROL di/dt FOR A MICROPROCESSOR
    2.
    发明授权
    MECHANISM TO CONTROL di/dt FOR A MICROPROCESSOR 有权
    机制用于控制DI / DT微处理器

    公开(公告)号：EP1307806B1

    公开(公告)日：2008-06-04

    申请号：EP01946437.9

    申请日：2001-06-14

    申请人： Intel Corporation

    发明人： GROCHOWSKI, Edward ,  SAGER, David ,  TIWARI, Vivek ,  YOUNG, Ian ,  AYERS, David, J.

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3237 ,  G06F1/28 ,  G06F1/3203 ,  Y02D10/128

    摘要： The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.

    MAGNETIC TUNNEL JUNCTION (MTJ) INTEGRATION ON BACKSIDE OF SILICON
    4.
    发明公开
    MAGNETIC TUNNEL JUNCTION (MTJ) INTEGRATION ON BACKSIDE OF SILICON 审中-公开

    公开(公告)号：EP3588502A3

    公开(公告)日：2020-03-25

    申请号：EP19175812.7

    申请日：2019-05-21

    申请人： Intel Corporation

    发明人： MANIPATRUNI, Sasikanth ,  GOSAVI, Tanay ,  YOUNG, Ian ,  NIKONOV, Dmitri

    IPC分类号： G11C11/16 ,  H01L21/768 ,  H01L27/06 ,  H01L27/22

    摘要： A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

    HYBRID CPU AND ANALOG IN-MEMORY ARTIFICIAL INTELLIGENCE PROCESSOR
    6.
    发明公开
    HYBRID CPU AND ANALOG IN-MEMORY ARTIFICIAL INTELLIGENCE PROCESSOR 审中-公开

    公开(公告)号：EP3686814A1

    公开(公告)日：2020-07-29

    申请号：EP19199361.7

    申请日：2019-09-24

    申请人： INTEL Corporation

    发明人： YOUNG, Ian ,  KRISHNAMURTHY, Ram ,  NIKONOV, Dmitri ,  MANIPATRUNI, Sasikanth ,  MATHURIYA, Amrita

    IPC分类号： G06N3/063 ,  G06N3/04

    摘要： Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) coupled to an analog in-memory artificial intelligence (AI) processor. A hybrid processor implementing the techniques according to an embodiment includes an AI processor configured to perform analog in-memory computations based on neural network (NN) weighting factors and input data provided by the CPU. The AI processor includes one or more NN layers. The NN layers include digital access circuits to receive data and weighting factors and to provide computational results. The NN layers also include memory circuits to store data and weights, and further include bit line processors and cross bit line processors to perform analog dot product computations between columns of the data memory circuits and the weight factor memory circuits. Some of the NN layers are configured as convolutional NN layers and others are configured as fully connected NN layers, according to some embodiments.

    FIELD EFFECT TRANSISTOR STRUCTURES USING GERMANIUM NANOWIRES
    9.
    发明公开
    FIELD EFFECT TRANSISTOR STRUCTURES USING GERMANIUM NANOWIRES 审中-公开
    场效应晶体管结构使用锗纳米线

    公开(公告)号：EP3238261A1

    公开(公告)日：2017-11-01

    申请号：EP14909251.2

    申请日：2014-12-24

    申请人： Intel Corporation

    发明人： KIM, Raseong ,  AVCI, Uygar ,  YOUNG, Ian

    IPC分类号： H01L29/772

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.

    摘要翻译： 描述了使用锗纳米线形成的场效应晶体管结构。 在一个示例中，该结构具有沿着预定约束取向在衬底上形成的锗纳米线，纳米线的第一端处的纳米线的第一掺杂区域以限定源极，纳米线的第二掺杂区域的第二端 以限定漏极以及在源极和漏极之间的纳米线上形成的栅极电介质。