公开(公告)号：EP3037976B1

公开(公告)日：2018-01-03

申请号：EP15195491.4

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： KWON, Kon-Woo ,  SOMASEKHAR, Dinesh ,  PARK, Sang Phill

IPC: G06F13/42

CPC classification number: H03M13/19 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

公开(公告)号：EP3716490A1

公开(公告)日：2020-09-30

申请号：EP20157895.2

申请日：2020-02-18

Applicant: INTEL Corporation

Inventor： WU, Wei ,  KOZHIKKOTTU, Vivek ,  SOMASEKHAR, Dinesh ,  STEPHAN, Jon ,  KWON, Kon-Woo

IPC: H03M13/19 ,  H03M13/17 ,  G06F11/10

Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K-2 (K-1) +1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

公开(公告)号：EP3037976A1

公开(公告)日：2016-06-29

申请号：EP15195491.4

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： KWON, Kon-Woo ,  SOMASEKHAR, Dinesh ,  PARK, Sang Phill

IPC: G06F13/42

CPC classification number: H03M13/19 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

Abstract translation: 描述与OR链接总线的增强数据总线反相（EDBI）编码有关的方法和设备。 在一个实施例中，总线上的输入数据至少部分地基于总线上的下一个数据值是否将从有效值转换到停止状态的确定进行编码。 还公开了其它实施例。