公开(公告)号：EP3353959A1

公开(公告)日：2018-08-01

申请号：EP16849732.9

申请日：2016-09-23

申请人： INTEL Corporation

发明人： TAMIR, Eliezer ,  FRIEDMAN, Ben-Zion ,  LEVIN, Itamar

IPC分类号： H04L12/28 ,  H04L29/10 ,  H04L12/931

CPC分类号： H04L67/145 ,  H04L12/28 ,  H04L41/0816 ,  H04L47/24 ,  H04L47/266 ,  H04L47/30 ,  H04L49/9068 ,  H04L67/025 ,  H04L69/24 ,  H04L69/322 ,  H04L69/323 ,  H04L69/324

摘要： Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.

公开(公告)号：EP4264896A1

公开(公告)日：2023-10-25

申请号：EP21907371.5

申请日：2021-09-10

申请人： Intel Corporation

发明人： LEVIN, Itamar ,  GRAFI, Tali Warshavsky ,  CUSMAI, Marco ,  BALANKUTTY, Ajay ,  SHIVA KIRAN, Fnu ,  COHEN, Ariel

IPC分类号： H04L25/03

公开(公告)号：EP4199440A1

公开(公告)日：2023-06-21

申请号：EP22206895.9

申请日：2022-11-11

申请人： INTEL Corporation

发明人： RAN, Adee Ofir ,  LEVIN, Itamar

IPC分类号： H04L25/03 ,  H04L25/497

摘要： Sampling circuitry for receiving an analog signal from photodetector circuitry and generating a sample analog signal. Equalization circuitry for generating an equalized signal comprising first and second sample values corresponding with a cursor tap and a first postcursor tap, and one or more third sample values corresponding with taps other than the cursor tap and the first postcursor tap. In the equalized signal, amplitudes of the first and second sample values are substantially equal while the third sample values are attenuated relative to the first and second sample values. The first and second sample values correspond with two or more first symbols of a first alphabet. Data slicer and modulo circuitry to generate a data signal based on the equalized signal and perform a modulo operation on the two or more first symbols and to generate one or more second symbols. The second symbols are according to a second alphabet.

公开(公告)号：EP3235203A1

公开(公告)日：2017-10-25

申请号：EP15870558.2

申请日：2015-11-12

申请人： Intel Corporation

发明人： LAUFER, Amir ,  LEVIN, Itamar

IPC分类号： H04L25/03 ,  H04L25/08

CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/03579

摘要： Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.

摘要翻译： 描述了包括具有第一DFE抽头路径和非第一DFE抽头路径的判定反馈均衡器（DFE）的设备，其中DFE在非第一DFE抽头路径的信号路径中包括可变延迟电路。 在一些实施例中，提供了一种装置，其包括：夏天; 一台切片机接受来自夏季的输入; 用于取消第一后标志的第一反馈回路，所述第一反馈回路通过将所述限幅器耦合到所述夏季而形成回路; 以及用于取消第二后标的第二反馈回路，所述第二反馈回路通过将所述第一反馈回路的输入耦合到所述加法器而形成回路，其中所述第二反馈回路在其输入处具有可编程延迟。