公开(公告)号：EP4202604A1

公开(公告)日：2023-06-28

申请号：EP22208942.7

申请日：2022-11-22

申请人： Intel Corporation

发明人： MOZAK, Christopher P. ,  ROYER, Robert J. Jr. ,  MARTIN, Aaron ,  THOMAS, Alex P. ,  LEVY, Tomer ,  LUPOVICH, Noam

IPC分类号： G06F1/324 ,  G11C11/406

摘要： In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.

公开(公告)号：EP3417455A1

公开(公告)日：2018-12-26

申请号：EP17753613.3

申请日：2017-01-17

申请人： Intel Corporation

发明人： MANSURI, Mozhgan ,  MARTIN, Aaron ,  MCCALL, James A.

IPC分类号： G11C11/4076 ,  G11C7/22 ,  H03K3/03 ,  G05F1/575

CPC分类号： G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

摘要： Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

公开(公告)号：EP3014772A1

公开(公告)日：2016-05-04

申请号：EP14818656.2

申请日：2014-06-19

申请人： Intel Corporation

发明人： MOZAK, Christopher P. ,  TRIVEDI, Ritesh B. ,  MCCALL, James A. ,  MARTIN, Aaron

IPC分类号： H03K19/0175 ,  H04L25/02

CPC分类号： H02M3/158 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  H04L25/0276 ,  H04L25/029

摘要： A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

摘要翻译： 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括用于响应于逻辑高来上拉传输线的p型驱动元件，以及n型驱动器元件，用于响应于逻辑低来拉低传输线。 电压调节器耦合在驱动器元件之一和相应的电压基准之间以减小传输线接口电路的电压摆幅。