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公开(公告)号：EP3014772A1
公开(公告)日：2016-05-04
申请号：EP14818656.2
申请日：2014-06-19
申请人： Intel Corporation
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H02M3/158 , G11C7/1057 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/105 , H04L25/0276 , H04L25/029
摘要： A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.
摘要翻译： 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括用于响应于逻辑高来上拉传输线的p型驱动元件，以及n型驱动器元件，用于响应于逻辑低来拉低传输线。 电压调节器耦合在驱动器元件之一和相应的电压基准之间以减小传输线接口电路的电压摆幅。
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公开(公告)号：EP3238345A1
公开(公告)日：2017-11-01
申请号：EP15873988.8
申请日：2015-11-23
申请人： Intel Corporation
IPC分类号： H03M13/00
CPC分类号： G06F13/4282 , G06F13/1668 , G06F13/28 , G06F21/79 , Y02D10/14 , Y02D10/151
摘要： An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.
摘要翻译： I / O接口支持加扰，其中加扰可以包括加扰码的非线性加扰，或加扰码的动态总线倒置，或加扰码的选定位的选择性切换，或这些的组合。 发送设备包括扰码器，并且接收设备包括解扰器。 扰码器和解扰器都生成通过应用上述一种或多种技术而修改的线性反馈扰码。 修改的扰码可以使得相对于先前的扰码输出来说，少于一半的扰码输出位被切换。 扰码器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收的信号。
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公开(公告)号：EP4202604A1
公开(公告)日：2023-06-28
申请号：EP22208942.7
申请日：2022-11-22
申请人： Intel Corporation
发明人： MOZAK, Christopher P. , ROYER, Robert J. Jr. , MARTIN, Aaron , THOMAS, Alex P. , LEVY, Tomer , LUPOVICH, Noam
IPC分类号： G06F1/324 , G11C11/406
摘要： In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.
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4.发明公开
公开(公告)号：EP2939239A1
公开(公告)日：2015-11-04
申请号：EP13868489.9
申请日：2013-06-24
申请人： Intel Corporation
IPC分类号： G11C11/406 , G11C11/402
CPC分类号： G11C7/02 , G11C11/40 , G11C11/40611 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2211/4062
摘要： A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.
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公开(公告)号：EP3533058A1
公开(公告)日：2019-09-04
申请号：EP17864379.7
申请日：2017-10-30
申请人： Intel Corporation
发明人： COX, Christopher E. , BAINS, Kuljit , MOZAK, Christopher P. , MCCALL, James A. , VASANTH, Akshith , NALE, Bill
IPC分类号： G11C11/4096 , G11C11/4074 , G11C7/10
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6.发明公开
公开(公告)号：EP2920664A1
公开(公告)日：2015-09-23
申请号：EP13854421.8
申请日：2013-06-10
申请人： Intel Corporation
摘要： Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.
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7.发明公开ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER 审中-公开ROBUSTER SPEICHERLINKTEST MITHILEL EINES SPEICHERCONTROLLERS
公开(公告)号：EP2519953A2
公开(公告)日：2012-11-07
申请号：EP10841479.8
申请日：2010-12-10
申请人： Intel Corporation
发明人： SPRY, Bryan L. , SCHOENBORN, Theodore Z. , ABRAHAM, Philip , MOZAK, Christopher P. , ELLIS, David G. , NEJEDLO, Jay J. , QUERBACH, Bruce , GREENFIELD, Zvika , GHATTAS, Rony , THOLIYIL, Jayasekhar , LUCAS, Charles D. , YUNKER, Christopher E.
IPC分类号： G11C29/10
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译： 引入了用于内存链接的REUT（强大的电气统一测试），可以加速测试，开发和调试。 此外，它提供了具有足够的性能的训练钩子，以供BIOS使用，以训练以前的实现中不可能的参数和条件。 还公开了地址图案生成电路。
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公开(公告)号：EP3901952A1
公开(公告)日：2021-10-27
申请号：EP21177402.1
申请日：2017-10-30
申请人： Intel Corporation
发明人： COX, Christopher E. , BAINS, Kuljit , MOZAK, Christopher P. , MCCALL, James A. , VASANTH, Akshith , NALE, Bill
IPC分类号： G11C11/406 , G11C7/22 , G11C7/10 , G11C11/4093
摘要： A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
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公开(公告)号：EP3840224A1
公开(公告)日：2021-06-23
申请号：EP20194495.6
申请日：2020-09-04
申请人： INTEL Corporation
发明人： MOZAK, Christopher P. , LI, Ralph S. , LIM, Chin Wah , ELASSAL, Mahmoud , BALAKRISHNAN, Anant , ALI, Isaac
摘要： Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.
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