公开(公告)号：EP3552108A1

公开(公告)日：2019-10-16

申请号：EP16923787.2

申请日：2016-12-12

申请人： Intel Corporation

发明人： BRANDT, Jason W. ,  CHAPPELL, Robert S. ,  CORBAL, Jesus ,  GROCHOWSKI, Edward T. ,  GUNTHER, Stephen H. ,  GUY, Buford M. ,  HUFF, Thomas R. ,  HUGHES, Christopher J. ,  OULD-AHMED-VALL, Elmoustapha ,  SINGHAL, Ronak ,  SOTOUDEH, Seyed Yahya ,  TOLL, Bret L. ,  RAPPOPORT, Lihu ,  PAPWORTH, David ,  ALLEN, James D.

IPC分类号： G06F12/0817

公开(公告)号：EP3889787A1

公开(公告)日：2021-10-06

申请号：EP21168711.6

申请日：2016-12-12

申请人： Intel Corporation

发明人： BRANDT, Jason W. ,  CHAPPELL, Robert S. ,  CORBAL, Jesus ,  GROCHOWSKI, Edward T. ,  GUNTHER, Stephen H. ,  GUY, Buford M. ,  HUFF, Thomas R. ,  HUGHES, Christopher J. ,  OULD-AHMED-VALL, Elmoustapha ,  SINGHAL, Ronak ,  SOTOUDEH, Seyed Yahya ,  TOLL, Bret L. ,  RAPPOPORT, Lihu ,  PAPWORTH, David ,  ALLEN, James D.

IPC分类号： G06F12/0808 ,  G06F12/0817 ,  G06F12/0831

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.