公开(公告)号：EP3314407B1

公开(公告)日：2020-11-04

申请号：EP16815015.9

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： GROCHOWSKI, Edward T. ,  RYVCHIN, Galina ,  BEHAR, Michael

IPC: G06F9/30

公开(公告)号：EP4089531A1

公开(公告)日：2022-11-16

申请号：EP22180798.5

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/38 ,  G06F12/08

Abstract: The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

公开(公告)号：EP4398113A3

公开(公告)日：2024-11-06

申请号：EP24178028.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

Abstract: The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.

公开(公告)号：EP4398113A2

公开(公告)日：2024-07-10

申请号：EP24178028.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F12/08

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/4411 ,  G06F9/45504 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/30181 ,  G06F9/30076 ,  Y02D10/00 ,  G06F9/38585 ,  G06F9/3858

Abstract: The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.

公开(公告)号：EP3292630A1

公开(公告)日：2018-03-14

申请号：EP16789728.9

申请日：2016-04-06

Applicant: INTEL Corporation

Inventor： VAN DALEN, Edwin Jan ,  WEZELENBURG, Martinus C. ,  ROOS, Steven ,  GROCHOWSKI, Edward T. ,  MAOR, Moshe

IPC: H03H17/02 ,  H03H17/06

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3893 ,  G06F9/455 ,  H03H17/0202 ,  H03H17/06 ,  H03H2017/0298

Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

公开(公告)号：EP4120070A1

公开(公告)日：2023-01-18

申请号：EP22193012.6

申请日：2016-12-31

Applicant: INTEL Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/30

Abstract: The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.

公开(公告)号：EP3552108A1

公开(公告)日：2019-10-16

申请号：EP16923787.2

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： BRANDT, Jason W. ,  CHAPPELL, Robert S. ,  CORBAL, Jesus ,  GROCHOWSKI, Edward T. ,  GUNTHER, Stephen H. ,  GUY, Buford M. ,  HUFF, Thomas R. ,  HUGHES, Christopher J. ,  OULD-AHMED-VALL, Elmoustapha ,  SINGHAL, Ronak ,  SOTOUDEH, Seyed Yahya ,  TOLL, Bret L. ,  RAPPOPORT, Lihu ,  PAPWORTH, David ,  ALLEN, James D.

IPC: G06F12/0817

公开(公告)号：EP3336693A1

公开(公告)日：2018-06-20

申请号：EP17202192.5

申请日：2017-11-16

Applicant: Intel Corporation

Inventor： MISHRA, Asit K. ,  MARR, Deborah T. ,  GROCHOWSKI, Edward T.

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F3/0614 ,  G06F3/0646 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3877 ,  G06F2212/1016

Abstract: First elements of a dense vector to be multiplied with first elements of a first row of a sparse array may be determined. The determined first elements of the dense vector may be written into a memory. A dot product for the first elements of the sparse array and the first elements of the dense vector may be calculated in a plurality of increments by multiplying a subset of the first elements of the sparse array and a corresponding subset of the first elements of the dense vector. A sequence number may be updated after each increment is completed to identify a column number and/or a row number of the sparse array for which the dot product calculations have been completed.

公开(公告)号：EP3889787A1

公开(公告)日：2021-10-06

申请号：EP21168711.6

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： BRANDT, Jason W. ,  CHAPPELL, Robert S. ,  CORBAL, Jesus ,  GROCHOWSKI, Edward T. ,  GUNTHER, Stephen H. ,  GUY, Buford M. ,  HUFF, Thomas R. ,  HUGHES, Christopher J. ,  OULD-AHMED-VALL, Elmoustapha ,  SINGHAL, Ronak ,  SOTOUDEH, Seyed Yahya ,  TOLL, Bret L. ,  RAPPOPORT, Lihu ,  PAPWORTH, David ,  ALLEN, James D.

IPC: G06F12/0808 ,  G06F12/0817 ,  G06F12/0831

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：EP3812900A1

公开(公告)日：2021-04-28

申请号：EP20207505.7

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： SANKARAN, Rajesh M. ,  NEIGER, Gilbert ,  RANGANATHAN, Narayan ,  VAN DOREN, Stephen R. ,  NUZMAN, Joseph ,  MCDONNELL, Niall D. ,  O'HANLON, Michael A. ,  MOSUR, Lokpraveen B. ,  DRYSDALE, Tracy Garrett ,  NURVITADHI, Eriko ,  MISHRA, Asit K. ,  VENKATESH, Ganesh ,  MARR, Deborah T. ,  CARTER, Nicholas P. ,  PEARCE, Jonathan D. ,  GROCHOWSKI, Edward T. ,  GRECO, Richard J. ,  VALENTINE, Robert ,  CORBAL, Jesus ,  FLETCHER, Thomas D. ,  BRADFORD, Dennis R. ,  MANLEY, Dwight P. ,  CHARNEY, Mark J. ,  COOK, Jeffrey J. ,  CAPRIOLI, Paul ,  YAMADA, Koichi ,  GLOSSOP, Kent D. ,  SHEFFIELD, David B.

IPC: G06F9/48 ,  G06F9/38

Abstract: The present disclosure provides apparatus comprising a silicon interposer, a communication fabric, an accelerator die comprising a plurality of computing elements to simultaneously perform operations on a plurality of matrix data elements. The apparatus comprising a plurality of dot-product engines, the plurality of dot-product engines to compute a plurality of dot products on the matrix data elements to generate a plurality of result matrix data elements, a buffer or cache to store a plurality of matrix data elements a memory controller coupled to the communication fabric and a stacked DRAM that stacks a plurality of DRAM dies vertically on the silicon interposer substrate coupled to the accelerator die.