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公开(公告)号：EP2619675B1
公开(公告)日：2018-08-22
申请号：EP11827736.7
申请日：2011-09-26
申请人： Intel Corporation
发明人： HINTON, Glenn , RAMANUJAN, Raj , CAPE, Scott J. , PARTHASARATHY, Madhavan , ZIMMERMAN, David , DOWNER, Wayne A. , PARTHASARATHY, Rajesh , SMITH, Larry O. , CHAPPELL, Robert S. , SWAMINATHAN, Muthukumar , MOGA, Adrian C.
IPC分类号： G06F12/1009 , G06F12/1027 , G06F9/06 , G06F12/00 , G06F13/14 , G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
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公开(公告)号：EP3647945A1
公开(公告)日：2020-05-06
申请号：EP19183503.2
申请日：2019-06-28
申请人： Intel Corporation
发明人： BRANDT, Jason W. , GUPTA, Deepak K. , BRANCO, Rodrigo , NUZMAN, Joseph , CHAPPELL, Robert S. , GHETIE, Sergiu , POWIERTOWSKI, Wojciech , STARK IV, Jared W. , SABBA, Ariel , CAPE, Scott J. , SHAFI, Hisham , RAPPOPORT, Lihu , BERGER, Yair , BOBHOLZ, Scott P. , HOLZSTEIN, Gilad , DALVI, Sagar V. , BIJLANI, Yogesh
摘要： Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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公开(公告)号：EP3552108A1
公开(公告)日：2019-10-16
申请号：EP16923787.2
申请日：2016-12-12
申请人： Intel Corporation
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
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公开(公告)号：EP3889787A1
公开(公告)日：2021-10-06
申请号：EP21168711.6
申请日：2016-12-12
申请人： Intel Corporation
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0808 , G06F12/0817 , G06F12/0831
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
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公开(公告)号：EP2619675A2
公开(公告)日：2013-07-31
申请号：EP11827736.7
申请日：2011-09-26
申请人： Intel Corporation
发明人： HINTON, Glenn , RAMANUJAN, Raj , CAPE, Scott J. , PARTHASARATHY, Madhavan , ZIMMERMAN, David , DOWNER, Wayne A. , PARTHASARATHY, Rajesh , SMITH, Larry O. , CHAPPELL, Robert S. , SWAMINATHAN, Muthukumar , MOGA, Adrian C.
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
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